[CodeGen][MIR] Support parsing of scalable vectors in MIR #70893
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
michaelmaitland
requested review from
arsenm,
mshockwave,
tschuett,
topperc and
sdesmalen-arm
arsenm
reviewed
Nov 1, 2023
topperc
reviewed
Nov 1, 2023
topperc
reviewed
Nov 1, 2023
topperc
reviewed
Nov 1, 2023
tschuett
reviewed
Nov 1, 2023
This patch builds on the support for vectors by adding ability to parse scalable vectors in MIR.
michaelmaitland
force-pushed
the
scalable-mir
branch
from
d5e11a6 to
538e6a1
Compare
topperc
reviewed
Nov 2, 2023
| lex(); | ||
| } | ||
|
|
||
| auto GetError = [this, &HasVScale, Loc]() { |
There was a problem hiding this comment.
If you capture Loc by value here, I don't think it update when lex() is called. So the location will be stale.
There was a problem hiding this comment.
Oh nevermind. Loc is passed as an argument and not coming from lex().
arsenm
reviewed
Nov 2, 2023
| if (HasVScale) | ||
| return error( | ||
| Loc, "expected <vscale x M x sN> or <vscale M x pA> for vector type"); | ||
| else |
michaelmaitland
added a commit
that referenced
this pull request
Nov 7, 2023
#70881) …gSizeInBits This patch changes getRegSizeInBits to return a TypeSize instead of an unsigned in the case that a virtual register has a scalable LLT. In the case that register is physical, a Fixed TypeSize is returned. The MachineVerifier pass is updated to allow copies between fixed and scalable operands as long as the Src size will fit into the Dest size. This is a precommit which will be stacked on by a change to GISel to generate COPYs with a scalable destination but a fixed size source. This patch is stacked on #70893 for the ability to use scalable vector types in MIR tests.
qihangkong
pushed a commit
to rvgpu/llvm
that referenced
this pull request
Apr 18, 2024
…… (#70881) …gSizeInBits This patch changes getRegSizeInBits to return a TypeSize instead of an unsigned in the case that a virtual register has a scalable LLT. In the case that register is physical, a Fixed TypeSize is returned. The MachineVerifier pass is updated to allow copies between fixed and scalable operands as long as the Src size will fit into the Dest size. This is a precommit which will be stacked on by a change to GISel to generate COPYs with a scalable destination but a fixed size source. This patch is stacked on llvm/llvm-project#70893 for the ability to use scalable vector types in MIR tests.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This patch builds on the support for vectors by adding ability to parse scalable vectors in MIR.