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[RISCV] Add MinimumJumpTableEntries to TuneInfo #72963

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Merged
merged 2 commits into from
Nov 23, 2023
Merged

[RISCV] Add MinimumJumpTableEntries to TuneInfo #72963

merged 2 commits into from
Nov 23, 2023

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wangpc-pp
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This is like what AArch64 has done in #71166 except that we don't
handle HasMinSize case now.

@wangpc-pp wangpc-pp requested review from topperc, dtcxzyw and asb November 21, 2023 07:15
@llvmbot
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llvmbot commented Nov 21, 2023

@llvm/pr-subscribers-backend-risc-v

Author: Wang Pengcheng (wangpc-pp)

Changes

This is like what AArch64 has done in #71166 except that we don't
handle HasMinSize case now.

Full diff: https://github.com/llvm/llvm-project/pull/72963.diff

6 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+5-2)
  • (modified) llvm/lib/Target/RISCV/RISCVISelLowering.h (+2)
  • (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+4-1)
  • (modified) llvm/lib/Target/RISCV/RISCVSubtarget.cpp (+10)
  • (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+4)
  • (modified) llvm/test/CodeGen/RISCV/jumptable.ll (+276)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c054f53e62849e0..d9af69b3683b8fe 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1358,8 +1358,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment());
   setPrefLoopAlignment(Subtarget.getPrefLoopAlignment());
 
-  setMinimumJumpTableEntries(5);
-
   // Jumps are expensive, compared to logic
   setJumpIsExpensive();
 
@@ -19630,6 +19628,11 @@ RISCVTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
     return SDValue();
   return TargetLowering::buildSDIVPow2WithCMov(N, Divisor, DAG, Created);
 }
+
+unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
+  return Subtarget.getMinimumJumpTableEntries();
+}
+
 namespace llvm::RISCVVIntrinsicsTable {
 
 #define GET_RISCVVIntrinsicsTable_IMPL
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 8f3ff4be22a2d1b..3d639310dd5e937 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -959,6 +959,8 @@ class RISCVTargetLowering : public TargetLowering {
 
   SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
                         SmallVectorImpl<SDNode *> &Created) const override;
+
+  unsigned getMinimumJumpTableEntries() const override;
 };
 
 namespace RISCV {
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 95389b07e9c1cdb..90ba99d3f845d38 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -19,6 +19,8 @@ class RISCVTuneInfo {
   bits<16> PrefetchDistance = 0;
   bits<16> MinPrefetchStride = 1;
   bits<32> MaxPrefetchIterationsAhead = -1;
+
+  bits<32> MinimumJumpTableEntries = 5;
 }
 
 def RISCVTuneInfoTable : GenericTable {
@@ -26,7 +28,8 @@ def RISCVTuneInfoTable : GenericTable {
   let CppTypeName = "RISCVTuneInfo";
   let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",
                 "CacheLineSize", "PrefetchDistance",
-                "MinPrefetchStride", "MaxPrefetchIterationsAhead"];
+                "MinPrefetchStride", "MaxPrefetchIterationsAhead",
+                "MinimumJumpTableEntries"];
 }
 
 def getRISCVTuneInfo : SearchIndex {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 3e6af1abc5d408b..c15290b9ff6b597 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -57,6 +57,10 @@ static cl::opt<unsigned> RISCVMaxBuildIntsCost(
 static cl::opt<bool> UseAA("riscv-use-aa", cl::init(true),
                            cl::desc("Enable the use of AA during codegen."));
 
+static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
+    "riscv-min-jump-table-entries", cl::init(5), cl::Hidden,
+    cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+
 void RISCVSubtarget::anchor() {}
 
 RISCVSubtarget &
@@ -189,3 +193,9 @@ void RISCVSubtarget::getPostRAMutations(
   /// Enable use of alias analysis during code generation (during MI
   /// scheduling, DAGCombine, etc.).
 bool RISCVSubtarget::useAA() const { return UseAA; }
+
+unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
+  return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
+             ? RISCVMinimumJumpTableEntries
+             : TuneInfo->MinimumJumpTableEntries;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index c135021333acabc..52f00f1f099030c 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -44,6 +44,8 @@ struct RISCVTuneInfo {
   uint16_t PrefetchDistance;
   uint16_t MinPrefetchStride;
   unsigned MaxPrefetchIterationsAhead;
+
+  unsigned MinimumJumpTableEntries;
 };
 
 #define GET_RISCVTuneInfoTable_DECL
@@ -270,6 +272,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   unsigned getMaxPrefetchIterationsAhead() const override {
     return TuneInfo->MaxPrefetchIterationsAhead;
   };
+
+  unsigned getMinimumJumpTableEntries() const;
 };
 } // End llvm namespace
 
diff --git a/llvm/test/CodeGen/RISCV/jumptable.ll b/llvm/test/CodeGen/RISCV/jumptable.ll
index 30c1ba0b542c856..2b5500920a32acb 100644
--- a/llvm/test/CodeGen/RISCV/jumptable.ll
+++ b/llvm/test/CodeGen/RISCV/jumptable.ll
@@ -11,6 +11,18 @@
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-MEDIUM
 ; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-PIC
+; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-SMALL-7-ENTRIES
+; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-MEDIUM-7-ENTRIES
+; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-PIC-7-ENTRIES
+; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-SMALL-7-ENTRIES
+; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-MEDIUM-7-ENTRIES
+; RUN: llc -mtriple=riscv64 -relocation-model=pic -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-PIC-7-ENTRIES
 
 define void @below_threshold(i32 signext %in, ptr %out) nounwind {
 ; CHECK-LABEL: below_threshold:
@@ -277,6 +289,270 @@ define void @above_threshold(i32 signext %in, ptr %out) nounwind {
 ; RV64I-PIC-NEXT:    sw a0, 0(a1)
 ; RV64I-PIC-NEXT:  .LBB1_9: # %exit
 ; RV64I-PIC-NEXT:    ret
+;
+; RV32I-SMALL-7-ENTRIES-LABEL: above_threshold:
+; RV32I-SMALL-7-ENTRIES:       # %bb.0: # %entry
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 3
+; RV32I-SMALL-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
+; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.1: # %entry
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 1
+; RV32I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
+; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.2: # %entry
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 2
+; RV32I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
+; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.3: # %entry
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 3
+; RV32I-SMALL-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.4: # %bb3
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 2
+; RV32I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_5: # %entry
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 4
+; RV32I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
+; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.6: # %entry
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 5
+; RV32I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
+; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.7: # %entry
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a2, 6
+; RV32I-SMALL-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV32I-SMALL-7-ENTRIES-NEXT:  # %bb.8: # %bb6
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 200
+; RV32I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 4
+; RV32I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 1
+; RV32I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 3
+; RV32I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
+; RV32I-SMALL-7-ENTRIES-NEXT:    li a0, 100
+; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_13: # %exit
+; RV32I-SMALL-7-ENTRIES-NEXT:    sw a0, 0(a1)
+; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_14: # %exit
+; RV32I-SMALL-7-ENTRIES-NEXT:    ret
+;
+; RV32I-MEDIUM-7-ENTRIES-LABEL: above_threshold:
+; RV32I-MEDIUM-7-ENTRIES:       # %bb.0: # %entry
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 3
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.1: # %entry
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 1
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.2: # %entry
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 2
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.3: # %entry
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 3
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.4: # %bb3
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 2
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_5: # %entry
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 4
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.6: # %entry
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 5
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.7: # %entry
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 6
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  # %bb.8: # %bb6
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 200
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 4
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 1
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 3
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a0, 100
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_13: # %exit
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    sw a0, 0(a1)
+; RV32I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_14: # %exit
+; RV32I-MEDIUM-7-ENTRIES-NEXT:    ret
+;
+; RV32I-PIC-7-ENTRIES-LABEL: above_threshold:
+; RV32I-PIC-7-ENTRIES:       # %bb.0: # %entry
+; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 3
+; RV32I-PIC-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
+; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.1: # %entry
+; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 1
+; RV32I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
+; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.2: # %entry
+; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 2
+; RV32I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
+; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.3: # %entry
+; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 3
+; RV32I-PIC-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.4: # %bb3
+; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 2
+; RV32I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_5: # %entry
+; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 4
+; RV32I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
+; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.6: # %entry
+; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 5
+; RV32I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
+; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.7: # %entry
+; RV32I-PIC-7-ENTRIES-NEXT:    li a2, 6
+; RV32I-PIC-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV32I-PIC-7-ENTRIES-NEXT:  # %bb.8: # %bb6
+; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 200
+; RV32I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
+; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 4
+; RV32I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
+; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 1
+; RV32I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
+; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 3
+; RV32I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
+; RV32I-PIC-7-ENTRIES-NEXT:    li a0, 100
+; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_13: # %exit
+; RV32I-PIC-7-ENTRIES-NEXT:    sw a0, 0(a1)
+; RV32I-PIC-7-ENTRIES-NEXT:  .LBB1_14: # %exit
+; RV32I-PIC-7-ENTRIES-NEXT:    ret
+;
+; RV64I-SMALL-7-ENTRIES-LABEL: above_threshold:
+; RV64I-SMALL-7-ENTRIES:       # %bb.0: # %entry
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 3
+; RV64I-SMALL-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
+; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.1: # %entry
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 1
+; RV64I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
+; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.2: # %entry
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 2
+; RV64I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
+; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.3: # %entry
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 3
+; RV64I-SMALL-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.4: # %bb3
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 2
+; RV64I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_5: # %entry
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 4
+; RV64I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
+; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.6: # %entry
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 5
+; RV64I-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
+; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.7: # %entry
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a2, 6
+; RV64I-SMALL-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV64I-SMALL-7-ENTRIES-NEXT:  # %bb.8: # %bb6
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 200
+; RV64I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 4
+; RV64I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 1
+; RV64I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 3
+; RV64I-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
+; RV64I-SMALL-7-ENTRIES-NEXT:    li a0, 100
+; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_13: # %exit
+; RV64I-SMALL-7-ENTRIES-NEXT:    sw a0, 0(a1)
+; RV64I-SMALL-7-ENTRIES-NEXT:  .LBB1_14: # %exit
+; RV64I-SMALL-7-ENTRIES-NEXT:    ret
+;
+; RV64I-MEDIUM-7-ENTRIES-LABEL: above_threshold:
+; RV64I-MEDIUM-7-ENTRIES:       # %bb.0: # %entry
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 3
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.1: # %entry
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 1
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.2: # %entry
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 2
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.3: # %entry
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 3
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.4: # %bb3
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 2
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_5: # %entry
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 4
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.6: # %entry
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 5
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.7: # %entry
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a2, 6
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  # %bb.8: # %bb6
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 200
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 4
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 1
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 3
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    li a0, 100
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_13: # %exit
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    sw a0, 0(a1)
+; RV64I-MEDIUM-7-ENTRIES-NEXT:  .LBB1_14: # %exit
+; RV64I-MEDIUM-7-ENTRIES-NEXT:    ret
+;
+; RV64I-PIC-7-ENTRIES-LABEL: above_threshold:
+; RV64I-PIC-7-ENTRIES:       # %bb.0: # %entry
+; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 3
+; RV64I-PIC-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
+; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.1: # %entry
+; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 1
+; RV64I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
+; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.2: # %entry
+; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 2
+; RV64I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
+; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.3: # %entry
+; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 3
+; RV64I-PIC-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.4: # %bb3
+; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 2
+; RV64I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_5: # %entry
+; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 4
+; RV64I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
+; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.6: # %entry
+; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 5
+; RV64I-PIC-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
+; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.7: # %entry
+; RV64I-PIC-7-ENTRIES-NEXT:    li a2, 6
+; RV64I-PIC-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV64I-PIC-7-ENTRIES-NEXT:  # %bb.8: # %bb6
+; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 200
+; RV64I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
+; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 4
+; RV64I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
+; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 1
+; RV64I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
+; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 3
+; RV64I-PIC-7-ENTRIES-NEXT:    j .LBB1_13
+; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
+; RV64I-PIC-7-ENTRIES-NEXT:    li a0, 100
+; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_13: # %exit
+; RV64I-PIC-7-ENTRIES-NEXT:    sw a0, 0(a1)
+; RV64I-PIC-7-ENTRIES-NEXT:  .LBB1_14: # %exit
+; RV64I-PIC-7-ENTRIES-NEXT:    ret
 entry:
   switch i32 %in, label %exit [
     i32 1, label %bb1

@topperc topperc requested a review from mshockwave November 22, 2023 01:32
mshockwave
mshockwave approved these changes Nov 22, 2023
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LGTM w/ minor comment.
I'm fine with handling minsize in future patches.

@wangpc-pp
[RISCV] Add MinimumJumpTableEntries to TuneInfo
5a715e0 
This is like what AArch64 has done in llvm#71166 except that we don't
handle `HasMinSize` case now.
@wangpc-pp
fixup! [RISCV] Add MinimumJumpTableEntries to TuneInfo
04983a6 
Remove default value
@wangpc-pp wangpc-pp force-pushed the main-riscv-tune-min-jumptable-entries branch from dd80c3d to 04983a6 Compare November 23, 2023 06:04
@wangpc-pp wangpc-pp merged commit 5973272 into llvm:main Nov 23, 2023
@wangpc-pp wangpc-pp deleted the main-riscv-tune-min-jumptable-entries branch November 23, 2023 06:06
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@mshockwave mshockwave mshockwave approved these changes

@topperc topperc Awaiting requested review from topperc

@dtcxzyw dtcxzyw Awaiting requested review from dtcxzyw

@asb asb Awaiting requested review from asb

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@wangpc-pp @llvmbot @mshockwave