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Merged
SixWeining merged 1 commit into from
Dec 1, 2023
Merged

[LoongArch] Add some binary IR instructions testcases for LASX #74031

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122 changes: 122 additions & 0 deletions llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

define void @add_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: add_v32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvadd.b $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <32 x i8>, ptr %a0
%v1 = load <32 x i8>, ptr %a1
%v2 = add <32 x i8> %v0, %v1
store <32 x i8> %v2, ptr %res
ret void
}

define void @add_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: add_v16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvadd.h $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <16 x i16>, ptr %a0
%v1 = load <16 x i16>, ptr %a1
%v2 = add <16 x i16> %v0, %v1
store <16 x i16> %v2, ptr %res
ret void
}

define void @add_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: add_v8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvadd.w $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x i32>, ptr %a0
%v1 = load <8 x i32>, ptr %a1
%v2 = add <8 x i32> %v0, %v1
store <8 x i32> %v2, ptr %res
ret void
}

define void @add_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: add_v4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvadd.d $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x i64>, ptr %a0
%v1 = load <4 x i64>, ptr %a1
%v2 = add <4 x i64> %v0, %v1
store <4 x i64> %v2, ptr %res
ret void
}

define void @add_v32i8_31(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: add_v32i8_31:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvaddi.bu $xr0, $xr0, 31
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <32 x i8>, ptr %a0
%v1 = add <32 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>
store <32 x i8> %v1, ptr %res
ret void
}

define void @add_v16i16_31(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: add_v16i16_31:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvaddi.hu $xr0, $xr0, 31
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <16 x i16>, ptr %a0
%v1 = add <16 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>
store <16 x i16> %v1, ptr %res
ret void
}

define void @add_v8i32_31(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: add_v8i32_31:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvaddi.wu $xr0, $xr0, 31
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x i32>, ptr %a0
%v1 = add <8 x i32> %v0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
store <8 x i32> %v1, ptr %res
ret void
}

define void @add_v4i64_31(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: add_v4i64_31:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvaddi.du $xr0, $xr0, 31
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x i64>, ptr %a0
%v1 = add <4 x i64> %v0, <i64 31, i64 31, i64 31, i64 31>
store <4 x i64> %v1, ptr %res
ret void
}
178 changes: 178 additions & 0 deletions llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,178 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

define void @ashr_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: ashr_v32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvsra.b $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <32 x i8>, ptr %a0
%v1 = load <32 x i8>, ptr %a1
%v2 = ashr <32 x i8> %v0, %v1
store <32 x i8> %v2, ptr %res
ret void
}

define void @ashr_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: ashr_v16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvsra.h $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <16 x i16>, ptr %a0
%v1 = load <16 x i16>, ptr %a1
%v2 = ashr <16 x i16> %v0, %v1
store <16 x i16> %v2, ptr %res
ret void
}

define void @ashr_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: ashr_v8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvsra.w $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x i32>, ptr %a0
%v1 = load <8 x i32>, ptr %a1
%v2 = ashr <8 x i32> %v0, %v1
store <8 x i32> %v2, ptr %res
ret void
}

define void @ashr_v4i64(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: ashr_v4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvsra.d $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x i64>, ptr %a0
%v1 = load <4 x i64>, ptr %a1
%v2 = ashr <4 x i64> %v0, %v1
store <4 x i64> %v2, ptr %res
ret void
}

define void @ashr_v32i8_1(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: ashr_v32i8_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvsrai.b $xr0, $xr0, 1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <32 x i8>, ptr %a0
%v1 = ashr <32 x i8> %v0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
store <32 x i8> %v1, ptr %res
ret void
}

define void @ashr_v32i8_7(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: ashr_v32i8_7:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvsrai.b $xr0, $xr0, 7
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <32 x i8>, ptr %a0
%v1 = ashr <32 x i8> %v0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
store <32 x i8> %v1, ptr %res
ret void
}

define void @ashr_v16i16_1(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: ashr_v16i16_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvsrai.h $xr0, $xr0, 1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <16 x i16>, ptr %a0
%v1 = ashr <16 x i16> %v0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
store <16 x i16> %v1, ptr %res
ret void
}

define void @ashr_v16i16_15(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: ashr_v16i16_15:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvsrai.h $xr0, $xr0, 15
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <16 x i16>, ptr %a0
%v1 = ashr <16 x i16> %v0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
store <16 x i16> %v1, ptr %res
ret void
}

define void @ashr_v8i32_1(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: ashr_v8i32_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvsrai.w $xr0, $xr0, 1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x i32>, ptr %a0
%v1 = ashr <8 x i32> %v0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
store <8 x i32> %v1, ptr %res
ret void
}

define void @ashr_v8i32_31(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: ashr_v8i32_31:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvsrai.w $xr0, $xr0, 31
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x i32>, ptr %a0
%v1 = ashr <8 x i32> %v0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
store <8 x i32> %v1, ptr %res
ret void
}

define void @ashr_v4i64_1(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: ashr_v4i64_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvsrai.d $xr0, $xr0, 1
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x i64>, ptr %a0
%v1 = ashr <4 x i64> %v0, <i64 1, i64 1, i64 1, i64 1>
store <4 x i64> %v1, ptr %res
ret void
}

define void @ashr_v4i64_63(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: ashr_v4i64_63:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a1, 0
; CHECK-NEXT: xvsrai.d $xr0, $xr0, 63
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x i64>, ptr %a0
%v1 = ashr <4 x i64> %v0, <i64 63, i64 63, i64 63, i64 63>
store <4 x i64> %v1, ptr %res
ret void
}
34 changes: 34 additions & 0 deletions llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

define void @fadd_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: fadd_v8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvfadd.s $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
%v2 = fadd <8 x float> %v0, %v1
store <8 x float> %v2, ptr %res
ret void
}

define void @fadd_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: fadd_v4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvfadd.d $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
%v2 = fadd <4 x double> %v0, %v1
store <4 x double> %v2, ptr %res
ret void
}
34 changes: 34 additions & 0 deletions llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s

define void @fdiv_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: fdiv_v8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvfdiv.s $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
%v2 = fdiv <8 x float> %v0, %v1
store <8 x float> %v2, ptr %res
ret void
}

define void @fdiv_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: fdiv_v4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvld $xr0, $a2, 0
; CHECK-NEXT: xvld $xr1, $a1, 0
; CHECK-NEXT: xvfdiv.d $xr0, $xr1, $xr0
; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
%v2 = fdiv <4 x double> %v0, %v1
store <4 x double> %v2, ptr %res
ret void
}
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