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[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction #75582

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Dec 20, 2023
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[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction #75582

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[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction
XinWang10 Dec 15, 2023
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resolve comments
XinWang10 Dec 18, 2023
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XinWang10 Dec 18, 2023
4939541
resolve comment and fix 1 test
XinWang10 Dec 19, 2023
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XinWang10 Dec 19, 2023
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8 changes: 8 additions & 0 deletions llvm/lib/Target/X86/X86InstrAsmAlias.td
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Expand Up @@ -686,3 +686,11 @@ def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;
def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>;
def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;

// Aliases with explicit %xmm0
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
(SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
(SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;

def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
(SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>;
94 changes: 65 additions & 29 deletions llvm/lib/Target/X86/X86InstrSSE.td
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Expand Up @@ -6706,31 +6706,31 @@ let Constraints = "$src1 = $dst" in {

// FIXME: Is there a better scheduler class for SHA than WriteVecIMul?
multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
X86FoldableSchedWrite sched, bit UsesXMM0 = 0> {
def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2),
!if(UsesXMM0,
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
[!if(UsesXMM0,
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
T8PS, Sched<[sched]>;

def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2),
!if(UsesXMM0,
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
[!if(UsesXMM0,
(set VR128:$dst, (IntId VR128:$src1,
(memop addr:$src2), XMM0)),
(set VR128:$dst, (IntId VR128:$src1,
(memop addr:$src2))))]>, T8PS,
Sched<[sched.Folded, sched.ReadAfterFold]>;
X86FoldableSchedWrite sched, string Suffix = "", bit UsesXMM0 = 0> {
def rr#Suffix : I<Opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2),
!if(UsesXMM0,
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
[!if(UsesXMM0,
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
T8PS, Sched<[sched]>;

def rm#Suffix : I<Opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2),
!if(UsesXMM0,
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
[!if(UsesXMM0,
(set VR128:$dst, (IntId VR128:$src1,
(memop addr:$src2), XMM0)),
(set VR128:$dst, (IntId VR128:$src1,
(memop addr:$src2))))]>, T8PS,
Sched<[sched.Folded, sched.ReadAfterFold]>;
}

let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in {
def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
Expand All @@ -6757,19 +6757,55 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {

let Uses=[XMM0] in
defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2,
SchedWriteVecIMul.XMM, 1>;
SchedWriteVecIMul.XMM, "", 1>;

defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1,
SchedWriteVecIMul.XMM>;
defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2,
SchedWriteVecIMul.XMM>;
}

// Aliases with explicit %xmm0
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
(SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
(SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode] in {
def SHA1RNDS4rri_EVEX: Ii8<0xD4, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst,
(int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
(i8 timm:$src3)))]>,
EVEX_NoCD8, T_MAP4PS, Sched<[SchedWriteVecIMul.XMM]>;
def SHA1RNDS4rmi_EVEX: Ii8<0xD4, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst,
(int_x86_sha1rnds4 VR128:$src1,
(memop addr:$src2),
(i8 timm:$src3)))]>,
EVEX_NoCD8, T_MAP4PS,
Sched<[SchedWriteVecIMul.XMM.Folded,
SchedWriteVecIMul.XMM.ReadAfterFold]>;

defm SHA1NEXTE : SHAI_binop<0xD8, "sha1nexte", int_x86_sha1nexte,
SchedWriteVecIMul.XMM, "_EVEX">,
EVEX_NoCD8, T_MAP4PS;
defm SHA1MSG1 : SHAI_binop<0xD9, "sha1msg1", int_x86_sha1msg1,
SchedWriteVecIMul.XMM, "_EVEX">,
EVEX_NoCD8, T_MAP4PS;
defm SHA1MSG2 : SHAI_binop<0xDA, "sha1msg2", int_x86_sha1msg2,
SchedWriteVecIMul.XMM, "_EVEX">,
EVEX_NoCD8, T_MAP4PS;

let Uses=[XMM0] in
defm SHA256RNDS2 : SHAI_binop<0xDB, "sha256rnds2", int_x86_sha256rnds2,
SchedWriteVecIMul.XMM, "_EVEX", 1>,
EVEX_NoCD8, T_MAP4PS;

defm SHA256MSG1 : SHAI_binop<0xDC, "sha256msg1", int_x86_sha256msg1,
SchedWriteVecIMul.XMM, "_EVEX">,
EVEX_NoCD8, T_MAP4PS;
defm SHA256MSG2 : SHAI_binop<0xDD, "sha256msg2", int_x86_sha256msg2,
SchedWriteVecIMul.XMM, "_EVEX">,
EVEX_NoCD8, T_MAP4PS;
}

//===----------------------------------------------------------------------===//
// AES-NI Instructions
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10 changes: 10 additions & 0 deletions llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
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Should be better to use file/cpuid instead of file/instruction to organize the test?

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I have a justification...

We used to organize the test by cpuid. But the folder name apx here is the already about cpuid, and we have so many instructions for apx, if we put it into a test file, it would be very huge.

# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

# ATT: sha1msg1 %xmm13, %xmm12
# INTEL: sha1msg1 xmm12, xmm13
0x45,0x0f,0x38,0xc9,0xe5

# ATT: sha1msg1 291(%r28,%r29,4), %xmm12
# INTEL: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00
10 changes: 10 additions & 0 deletions llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

# ATT: sha1msg2 %xmm13, %xmm12
# INTEL: sha1msg2 xmm12, xmm13
0x45,0x0f,0x38,0xca,0xe5

# ATT: sha1msg2 291(%r28,%r29,4), %xmm12
# INTEL: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00
10 changes: 10 additions & 0 deletions llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

# ATT: sha1nexte %xmm13, %xmm12
# INTEL: sha1nexte xmm12, xmm13
0x45,0x0f,0x38,0xc8,0xe5

# ATT: sha1nexte 291(%r28,%r29,4), %xmm12
# INTEL: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00
10 changes: 10 additions & 0 deletions llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

# ATT: sha1rnds4 $123, %xmm13, %xmm12
# INTEL: sha1rnds4 xmm12, xmm13, 123
0x45,0x0f,0x3a,0xcc,0xe5,0x7b

# ATT: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
# INTEL: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b
10 changes: 10 additions & 0 deletions llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

# ATT: sha256msg1 %xmm13, %xmm12
# INTEL: sha256msg1 xmm12, xmm13
0x45,0x0f,0x38,0xcc,0xe5

# ATT: sha256msg1 291(%r28,%r29,4), %xmm12
# INTEL: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00
10 changes: 10 additions & 0 deletions llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

# ATT: sha256msg2 %xmm13, %xmm12
# INTEL: sha256msg2 xmm12, xmm13
0x45,0x0f,0x38,0xcd,0xe5

# ATT: sha256msg2 291(%r28,%r29,4), %xmm12
# INTEL: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00
10 changes: 10 additions & 0 deletions llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
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# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

# ATT: sha256rnds2 %xmm0, %xmm13, %xmm12
# INTEL: sha256rnds2 xmm12, xmm13, xmm0
0x45,0x0f,0x38,0xcb,0xe5

# ATT: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
# INTEL: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha1msg1-att.s
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s

# CHECK: sha1msg1 %xmm13, %xmm12
# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
sha1msg1 %xmm13, %xmm12

# CHECK: sha1msg1 291(%r28,%r29,4), %xmm12
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
sha1msg1 291(%r28,%r29,4), %xmm12
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha1msg1-intel.s
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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s

# CHECK: sha1msg1 xmm12, xmm13
# CHECK: encoding: [0x45,0x0f,0x38,0xc9,0xe5]
sha1msg1 xmm12, xmm13

# CHECK: sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd9,0xa4,0xac,0x23,0x01,0x00,0x00]
sha1msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha1msg2-att.s
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s

# CHECK: sha1msg2 %xmm13, %xmm12
# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5]
sha1msg2 %xmm13, %xmm12

# CHECK: sha1msg2 291(%r28,%r29,4), %xmm12
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00]
sha1msg2 291(%r28,%r29,4), %xmm12
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha1msg2-intel.s
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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s

# CHECK: sha1msg2 xmm12, xmm13
# CHECK: encoding: [0x45,0x0f,0x38,0xca,0xe5]
sha1msg2 xmm12, xmm13

# CHECK: sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xda,0xa4,0xac,0x23,0x01,0x00,0x00]
sha1msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha1nexte-att.s
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s

# CHECK: sha1nexte %xmm13, %xmm12
# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5]
sha1nexte %xmm13, %xmm12

# CHECK: sha1nexte 291(%r28,%r29,4), %xmm12
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00]
sha1nexte 291(%r28,%r29,4), %xmm12
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha1nexte-intel.s
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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s

# CHECK: sha1nexte xmm12, xmm13
# CHECK: encoding: [0x45,0x0f,0x38,0xc8,0xe5]
sha1nexte xmm12, xmm13

# CHECK: sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd8,0xa4,0xac,0x23,0x01,0x00,0x00]
sha1nexte xmm12, xmmword ptr [r28 + 4*r29 + 291]
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha1rnds4-att.s
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s

# CHECK: sha1rnds4 $123, %xmm13, %xmm12
# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b]
sha1rnds4 $123, %xmm13, %xmm12

# CHECK: sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b]
sha1rnds4 $123, 291(%r28,%r29,4), %xmm12
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha1rnds4-intel.s
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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s

# CHECK: sha1rnds4 xmm12, xmm13, 123
# CHECK: encoding: [0x45,0x0f,0x3a,0xcc,0xe5,0x7b]
sha1rnds4 xmm12, xmm13, 123

# CHECK: sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xd4,0xa4,0xac,0x23,0x01,0x00,0x00,0x7b]
sha1rnds4 xmm12, xmmword ptr [r28 + 4*r29 + 291], 123
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha256msg1-att.s
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s

# CHECK: sha256msg1 %xmm13, %xmm12
# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5]
sha256msg1 %xmm13, %xmm12

# CHECK: sha256msg1 291(%r28,%r29,4), %xmm12
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
sha256msg1 291(%r28,%r29,4), %xmm12
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha256msg1-intel.s
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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s

# CHECK: sha256msg1 xmm12, xmm13
# CHECK: encoding: [0x45,0x0f,0x38,0xcc,0xe5]
sha256msg1 xmm12, xmm13

# CHECK: sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdc,0xa4,0xac,0x23,0x01,0x00,0x00]
sha256msg1 xmm12, xmmword ptr [r28 + 4*r29 + 291]
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha256msg2-att.s
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s

# CHECK: sha256msg2 %xmm13, %xmm12
# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5]
sha256msg2 %xmm13, %xmm12

# CHECK: sha256msg2 291(%r28,%r29,4), %xmm12
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
sha256msg2 291(%r28,%r29,4), %xmm12
9 changes: 9 additions & 0 deletions llvm/test/MC/X86/apx/sha256msg2-intel.s
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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s

# CHECK: sha256msg2 xmm12, xmm13
# CHECK: encoding: [0x45,0x0f,0x38,0xcd,0xe5]
sha256msg2 xmm12, xmm13

# CHECK: sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdd,0xa4,0xac,0x23,0x01,0x00,0x00]
sha256msg2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
13 changes: 13 additions & 0 deletions llvm/test/MC/X86/apx/sha256rnds2-att.s
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s

# CHECK: sha256rnds2 %xmm0, %xmm13, %xmm12
# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5]
sha256rnds2 %xmm0, %xmm13, %xmm12

# CHECK: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12

# CHECK: sha256rnds2 %xmm0, 291(%r28,%r29,4), %xmm12
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
sha256rnds2 291(%r28,%r29,4), %xmm12
14 changes: 14 additions & 0 deletions llvm/test/MC/X86/apx/sha256rnds2-intel.s
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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s

# CHECK: sha256rnds2 xmm12, xmm13, xmm0
# CHECK: encoding: [0x45,0x0f,0x38,0xcb,0xe5]
sha256rnds2 xmm12, xmm13, xmm0

# CHECK: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0

# CHECK: sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291], xmm0
# CHECK: encoding: [0x62,0x1c,0x78,0x08,0xdb,0xa4,0xac,0x23,0x01,0x00,0x00]
sha256rnds2 xmm12, xmmword ptr [r28 + 4*r29 + 291]
2 changes: 1 addition & 1 deletion llvm/test/MC/X86/x86_64-asm-match.s
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Expand Up @@ -11,7 +11,7 @@
// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
// CHECK: Opcode result: complete match, selecting this opcode
// CHECK: AsmMatcher: found 2 encodings with mnemonic 'sha1rnds4'
// CHECK: AsmMatcher: found 4 encodings with mnemonic 'sha1rnds4'
// CHECK: Trying to match opcode SHA1RNDS4rri
// CHECK: Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:1): match success using generic matcher
// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
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7 changes: 7 additions & 0 deletions llvm/test/TableGen/x86-fold-tables.inc
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Expand Up @@ -1632,12 +1632,19 @@ static const X86FoldTableEntry Table2[] = {
{X86::SBB64rr, X86::SBB64rm, 0},
{X86::SBB8rr, X86::SBB8rm, 0},
{X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16},
{X86::SHA1MSG1rr_EVEX, X86::SHA1MSG1rm_EVEX, TB_ALIGN_16},
{X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16},
{X86::SHA1MSG2rr_EVEX, X86::SHA1MSG2rm_EVEX, TB_ALIGN_16},
{X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16},
{X86::SHA1NEXTErr_EVEX, X86::SHA1NEXTErm_EVEX, TB_ALIGN_16},
{X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16},
{X86::SHA1RNDS4rri_EVEX, X86::SHA1RNDS4rmi_EVEX, TB_ALIGN_16},
{X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16},
{X86::SHA256MSG1rr_EVEX, X86::SHA256MSG1rm_EVEX, TB_ALIGN_16},
{X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16},
{X86::SHA256MSG2rr_EVEX, X86::SHA256MSG2rm_EVEX, TB_ALIGN_16},
{X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16},
{X86::SHA256RNDS2rr_EVEX, X86::SHA256RNDS2rm_EVEX, TB_ALIGN_16},
{X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16},
{X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16},
{X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE},
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6 changes: 4 additions & 2 deletions llvm/utils/TableGen/X86FoldTablesEmitter.cpp
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Expand Up @@ -32,8 +32,10 @@ struct ManualMapEntry {
};

// List of instructions requiring explicitly aligned memory.
const char *ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS",
"MOVNTPD", "MOVNTDQ", "MOVNTDQA"};
const char *ExplicitAlign[] = {
"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS", "MOVNTPD",
"MOVNTDQ", "MOVNTDQA", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE",
"SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2"};

// List of instructions NOT requiring explicit memory alignment.
const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD",
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