[X86] Support APX promoted RAO-INT and MOVBE instructions #77431

XinWang10 · 2024-01-09T09:38:39Z

R16-R31 was added into GPRs in #70958,
This patch supports the promoted RAO-INT and MOVBE instructions in EVEX space.

RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4

llvmbot · 2024-01-09T09:39:07Z

@llvm/pr-subscribers-backend-x86

@llvm/pr-subscribers-mc

Author: None (XinWang10)

Changes

R16-R31 was added into GPRs in #70958,
This patch supports the promoted RAO-INT and MOVBEinstructions in EVEX space.

RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4

Patch is 35.47 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/77431.diff

12 Files Affected:

(modified) llvm/lib/Target/X86/X86InstrMisc.td (+53-1)
(modified) llvm/lib/Target/X86/X86InstrRAOINT.td (+18-9)
(modified) llvm/test/CodeGen/X86/movbe.ll (+122-24)
(modified) llvm/test/CodeGen/X86/raoint-intrinsics-32.ll (+21)
(modified) llvm/test/CodeGen/X86/raoint-intrinsics-64.ll (+21)
(added) llvm/test/MC/Disassembler/X86/apx/movbe.txt (+86)
(added) llvm/test/MC/Disassembler/X86/apx/rao-int.txt (+74)
(added) llvm/test/MC/X86/apx/movbe-att.s (+76)
(added) llvm/test/MC/X86/apx/movbe-intel.s (+73)
(added) llvm/test/MC/X86/apx/rao-int-att.s (+77)
(added) llvm/test/MC/X86/apx/rao-int-intel.s (+73)
(modified) llvm/test/TableGen/x86-fold-tables.inc (+3)

diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
index 97c625a64cfc0b..e48d0a2b63de29 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1090,7 +1090,7 @@ def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
 //===----------------------------------------------------------------------===//
 // MOVBE Instructions
 //
-let Predicates = [HasMOVBE] in {
+let Predicates = [HasMOVBE, NoEGPR] in {
   let SchedRW = [WriteALULd] in {
   def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
                     "movbe{w}\t{$src, $dst|$dst, $src}",
@@ -1121,6 +1121,58 @@ let Predicates = [HasMOVBE] in {
   }
 }
 
+let Predicates = [HasMOVBE, HasEGPR, In64BitMode] in {
+  let SchedRW = [WriteALULd] in {
+  def MOVBE16rm_EVEX : I<0x60, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
+                         "movbe{w}\t{$src, $dst|$dst, $src}",
+                         [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>,
+                       EVEX, NoCD8, T_MAP4, PD;
+  def MOVBE32rm_EVEX : I<0x60, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
+                         "movbe{l}\t{$src, $dst|$dst, $src}",
+                         [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>,
+                       EVEX, NoCD8, T_MAP4;
+  def MOVBE64rm_EVEX : RI<0x60, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
+                         "movbe{q}\t{$src, $dst|$dst, $src}",
+                         [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>,
+                       EVEX, NoCD8, T_MAP4;
+  }
+  let SchedRW = [WriteStore] in {
+  def MOVBE16mr_EVEX : I<0x61, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
+                         "movbe{w}\t{$src, $dst|$dst, $src}",
+                         [(store (bswap GR16:$src), addr:$dst)]>,
+                       EVEX, NoCD8, T_MAP4, PD;
+  def MOVBE32mr_EVEX : I<0x61, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+                         "movbe{l}\t{$src, $dst|$dst, $src}",
+                         [(store (bswap GR32:$src), addr:$dst)]>,
+                       EVEX, NoCD8, T_MAP4;
+  def MOVBE64mr_EVEX : RI<0x61, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
+                         "movbe{q}\t{$src, $dst|$dst, $src}",
+                         [(store (bswap GR64:$src), addr:$dst)]>,
+                       EVEX, NoCD8, T_MAP4;
+  }
+  let SchedRW = [WriteALU] in {
+  def MOVBE16rr_EVEX : I<0x61, MRMDestReg, (outs), (ins GR16:$dst, GR16:$src),
+                         "movbe{w}\t{$src, $dst|$dst, $src}", []>,
+                       EVEX, NoCD8, T_MAP4, PD;
+  def MOVBE32rr_EVEX : I<0x61, MRMDestReg, (outs), (ins GR32:$dst, GR32:$src),
+                         "movbe{l}\t{$src, $dst|$dst, $src}", []>,
+                       EVEX, NoCD8, T_MAP4;
+  def MOVBE64rr_EVEX : RI<0x61, MRMDestReg, (outs), (ins GR64:$dst, GR64:$src),
+                          "movbe{q}\t{$src, $dst|$dst, $src}", []>,
+                       EVEX, NoCD8, T_MAP4;
+
+  def MOVBE16rr_EVEX_REV : I<0x60, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
+                             "movbe{w}\t{$src, $dst|$dst, $src}", []>,
+                           EVEX, NoCD8, T_MAP4, PD;
+  def MOVBE32rr_EVEX_REV : I<0x60, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
+                             "movbe{l}\t{$src, $dst|$dst, $src}", []>,
+                           EVEX, NoCD8, T_MAP4;
+  def MOVBE64rr_EVEX_REV : RI<0x60, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
+                              "movbe{q}\t{$src, $dst|$dst, $src}", []>,
+                           EVEX, NoCD8, T_MAP4;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // RDRAND Instruction
 //
diff --git a/llvm/lib/Target/X86/X86InstrRAOINT.td b/llvm/lib/Target/X86/X86InstrRAOINT.td
index bc17b00f3573a9..c2f202bd616a51 100644
--- a/llvm/lib/Target/X86/X86InstrRAOINT.td
+++ b/llvm/lib/Target/X86/X86InstrRAOINT.td
@@ -25,21 +25,30 @@ def X86rao_xor  : SDNode<"X86ISD::AXOR", SDTRAOBinaryArith,
 def X86rao_and  : SDNode<"X86ISD::AAND", SDTRAOBinaryArith,
                          [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
-multiclass RAOINT_BASE<string OpcodeStr> {
+multiclass RAOINT_BASE<string OpcodeStr, string Suffix = ""> {
   let Predicates = [HasRAOINT] in
-    def 32mr : I<0xfc, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
-                 !strconcat("a", OpcodeStr, "{l}\t{$src, $dst|$dst, $src}"),
-                 [(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR32:$src)]>,
-               Sched<[WriteALURMW]>;
+    def 32mr#Suffix : I<0xfc, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+                        !strconcat("a", OpcodeStr, "{l}\t{$src, $dst|$dst, $src}"),
+                        [(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR32:$src)]>,
+                      Sched<[WriteALURMW]>;
 
   let Predicates = [HasRAOINT, In64BitMode] in
-    def 64mr : I<0xfc, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
-                 !strconcat("a", OpcodeStr, "{q}\t{$src, $dst|$dst, $src}"),
-                 [(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR64:$src)]>,
-               Sched<[WriteALURMW]>, REX_W;
+    def 64mr#Suffix : I<0xfc, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
+                        !strconcat("a", OpcodeStr, "{q}\t{$src, $dst|$dst, $src}"),
+                        [(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR64:$src)]>,
+                      Sched<[WriteALURMW]>, REX_W;
 }
 
+let Predicates = [HasRAOINT, NoEGPR] in {
 defm AADD : RAOINT_BASE<"add">, T8;
 defm AAND : RAOINT_BASE<"and">, T8, PD;
 defm AOR  : RAOINT_BASE<"or" >, T8, XD;
 defm AXOR : RAOINT_BASE<"xor">, T8, XS;
+}
+
+let Predicates = [HasRAOINT, HasEGPR, In64BitMode] in {
+defm AADD : RAOINT_BASE<"add", "_EVEX">, EVEX, NoCD8, T_MAP4;
+defm AAND : RAOINT_BASE<"and", "_EVEX">, EVEX, NoCD8, T_MAP4, PD;
+defm AOR  : RAOINT_BASE<"or", "_EVEX">, EVEX, NoCD8, T_MAP4, XD;
+defm AXOR : RAOINT_BASE<"xor", "_EVEX">, EVEX, NoCD8, T_MAP4, XS;
+}
diff --git a/llvm/test/CodeGen/X86/movbe.ll b/llvm/test/CodeGen/X86/movbe.ll
index ef22fcaf698ca1..60d98ce05a9d86 100644
--- a/llvm/test/CodeGen/X86/movbe.ll
+++ b/llvm/test/CodeGen/X86/movbe.ll
@@ -1,66 +1,164 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
 ; RUN: llc -mtriple=x86_64-linux -mcpu=atom < %s | FileCheck %s
 ; RUN: llc -mtriple=x86_64-linux -mcpu=slm < %s | FileCheck %s -check-prefix=SLM
+; RUN: llc -mtriple=x86_64-linux -mcpu=slm -mattr=+egpr --show-mc-encoding < %s | FileCheck %s -check-prefix=EGPR
 
 declare i16 @llvm.bswap.i16(i16) nounwind readnone
 declare i32 @llvm.bswap.i32(i32) nounwind readnone
 declare i64 @llvm.bswap.i64(i64) nounwind readnone
 
 define void @test1(ptr nocapture %x, i16 %y) nounwind {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movbew %si, (%rdi)
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    retq
+;
+; SLM-LABEL: test1:
+; SLM:       # %bb.0:
+; SLM-NEXT:    movbew %si, (%rdi)
+; SLM-NEXT:    retq
+;
+; EGPR-LABEL: test1:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    movbew %si, (%rdi) # EVEX TO LEGACY Compression encoding: [0x66,0x0f,0x38,0xf1,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   %bswap = call i16 @llvm.bswap.i16(i16 %y)
   store i16 %bswap, ptr %x, align 2
   ret void
-; CHECK-LABEL: test1:
-; CHECK: movbew %si, (%rdi)
-; SLM-LABEL: test1:
-; SLM: movbew   %si, (%rdi)
 }
 
 define i16 @test2(ptr %x) nounwind {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movbew (%rdi), %ax
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    retq
+;
+; SLM-LABEL: test2:
+; SLM:       # %bb.0:
+; SLM-NEXT:    movbew (%rdi), %ax
+; SLM-NEXT:    retq
+;
+; EGPR-LABEL: test2:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    movbew (%rdi), %ax # EVEX TO LEGACY Compression encoding: [0x66,0x0f,0x38,0xf0,0x07]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   %load = load i16, ptr %x, align 2
   %bswap = call i16 @llvm.bswap.i16(i16 %load)
   ret i16 %bswap
-; CHECK-LABEL: test2:
-; CHECK: movbew (%rdi), %ax
-; SLM-LABEL: test2:
-; SLM: movbew   (%rdi), %ax
 }
 
 define void @test3(ptr nocapture %x, i32 %y) nounwind {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movbel %esi, (%rdi)
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    retq
+;
+; SLM-LABEL: test3:
+; SLM:       # %bb.0:
+; SLM-NEXT:    movbel %esi, (%rdi)
+; SLM-NEXT:    retq
+;
+; EGPR-LABEL: test3:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    movbel %esi, (%rdi) # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xf1,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   %bswap = call i32 @llvm.bswap.i32(i32 %y)
   store i32 %bswap, ptr %x, align 4
   ret void
-; CHECK-LABEL: test3:
-; CHECK: movbel	%esi, (%rdi)
-; SLM-LABEL: test3:
-; SLM: movbel	%esi, (%rdi)
 }
 
 define i32 @test4(ptr %x) nounwind {
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movbel (%rdi), %eax
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    retq
+;
+; SLM-LABEL: test4:
+; SLM:       # %bb.0:
+; SLM-NEXT:    movbel (%rdi), %eax
+; SLM-NEXT:    retq
+;
+; EGPR-LABEL: test4:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    movbel (%rdi), %eax # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xf0,0x07]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   %load = load i32, ptr %x, align 4
   %bswap = call i32 @llvm.bswap.i32(i32 %load)
   ret i32 %bswap
-; CHECK-LABEL: test4:
-; CHECK: movbel	(%rdi), %eax
-; SLM-LABEL: test4:
-; SLM: movbel	(%rdi), %eax
 }
 
 define void @test5(ptr %x, i64 %y) nounwind {
+; CHECK-LABEL: test5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movbeq %rsi, (%rdi)
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    retq
+;
+; SLM-LABEL: test5:
+; SLM:       # %bb.0:
+; SLM-NEXT:    movbeq %rsi, (%rdi)
+; SLM-NEXT:    retq
+;
+; EGPR-LABEL: test5:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    movbeq %rsi, (%rdi) # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x38,0xf1,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   %bswap = call i64 @llvm.bswap.i64(i64 %y)
   store i64 %bswap, ptr %x, align 8
   ret void
-; CHECK-LABEL: test5:
-; CHECK: movbeq	%rsi, (%rdi)
-; SLM-LABEL: test5:
-; SLM: movbeq	%rsi, (%rdi)
 }
 
 define i64 @test6(ptr %x) nounwind {
+; CHECK-LABEL: test6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movbeq (%rdi), %rax
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    retq
+;
+; SLM-LABEL: test6:
+; SLM:       # %bb.0:
+; SLM-NEXT:    movbeq (%rdi), %rax
+; SLM-NEXT:    retq
+;
+; EGPR-LABEL: test6:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    movbeq (%rdi), %rax # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x38,0xf0,0x07]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   %load = load i64, ptr %x, align 8
   %bswap = call i64 @llvm.bswap.i64(i64 %load)
   ret i64 %bswap
-; CHECK-LABEL: test6:
-; CHECK: movbeq	(%rdi), %rax
-; SLM-LABEL: test6:
-; SLM: movbeq	(%rdi), %rax
 }
diff --git a/llvm/test/CodeGen/X86/raoint-intrinsics-32.ll b/llvm/test/CodeGen/X86/raoint-intrinsics-32.ll
index 9715c8f4c03489..20b27cd43f5701 100644
--- a/llvm/test/CodeGen/X86/raoint-intrinsics-32.ll
+++ b/llvm/test/CodeGen/X86/raoint-intrinsics-32.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+raoint | FileCheck %s --check-prefixes=X64
 ; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+raoint | FileCheck %s --check-prefixes=X86
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+raoint,+egpr --show-mc-encoding | FileCheck %s --check-prefixes=EGPR
 
 define void @test_int_x86_aadd32(ptr %A, i32 %B) {
 ; X64-LABEL: test_int_x86_aadd32:
@@ -14,6 +15,11 @@ define void @test_int_x86_aadd32(ptr %A, i32 %B) {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
 ; X86-NEXT:    aaddl %eax, (%ecx) # encoding: [0x0f,0x38,0xfc,0x01]
 ; X86-NEXT:    retl # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_aadd32:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    aaddl %esi, (%rdi) # EVEX TO LEGACY Compression encoding: [0x0f,0x38,0xfc,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   call void @llvm.x86.aadd32(ptr %A, i32 %B)
   ret  void
 }
@@ -31,6 +37,11 @@ define void @test_int_x86_aand32(ptr %A, i32 %B) {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
 ; X86-NEXT:    aandl %eax, (%ecx) # encoding: [0x66,0x0f,0x38,0xfc,0x01]
 ; X86-NEXT:    retl # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_aand32:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    aandl %esi, (%rdi) # EVEX TO LEGACY Compression encoding: [0x66,0x0f,0x38,0xfc,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   call void @llvm.x86.aand32(ptr %A, i32 %B)
   ret  void
 }
@@ -48,6 +59,11 @@ define void @test_int_x86_aor32(ptr %A, i32 %B) {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
 ; X86-NEXT:    aorl %eax, (%ecx) # encoding: [0xf2,0x0f,0x38,0xfc,0x01]
 ; X86-NEXT:    retl # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_aor32:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    aorl %esi, (%rdi) # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xfc,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   call void @llvm.x86.aor32(ptr %A, i32 %B)
   ret  void
 }
@@ -65,6 +81,11 @@ define void @test_int_x86_axor32(ptr %A, i32 %B) {
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
 ; X86-NEXT:    axorl %eax, (%ecx) # encoding: [0xf3,0x0f,0x38,0xfc,0x01]
 ; X86-NEXT:    retl # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_axor32:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    axorl %esi, (%rdi) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xfc,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   call void @llvm.x86.axor32(ptr %A, i32 %B)
   ret  void
 }
diff --git a/llvm/test/CodeGen/X86/raoint-intrinsics-64.ll b/llvm/test/CodeGen/X86/raoint-intrinsics-64.ll
index 9d4fec591b7629..6b684615a0261b 100644
--- a/llvm/test/CodeGen/X86/raoint-intrinsics-64.ll
+++ b/llvm/test/CodeGen/X86/raoint-intrinsics-64.ll
@@ -1,11 +1,17 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+raoint | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+raoint,+egpr | FileCheck %s --check-prefixes=EGPR
 
 define void @test_int_x86_aadd64(ptr %A, i64 %B) {
 ; X64-LABEL: test_int_x86_aadd64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    aaddq %rsi, (%rdi) # encoding: [0x48,0x0f,0x38,0xfc,0x37]
 ; X64-NEXT:    retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_aadd64:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    aaddq %rsi, (%rdi) # EVEX TO LEGACY Compression encoding: [0x48,0x0f,0x38,0xfc,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   call void @llvm.x86.aadd64(ptr %A, i64 %B)
   ret  void
 }
@@ -16,6 +22,11 @@ define void @test_int_x86_aand64(ptr %A, i64 %B) {
 ; X64:       # %bb.0:
 ; X64-NEXT:    aandq %rsi, (%rdi) # encoding: [0x66,0x48,0x0f,0x38,0xfc,0x37]
 ; X64-NEXT:    retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_aand64:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    aandq %rsi, (%rdi) # EVEX TO LEGACY Compression encoding: [0x66,0x48,0x0f,0x38,0xfc,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   call void @llvm.x86.aand64(ptr %A, i64 %B)
   ret  void
 }
@@ -26,6 +37,11 @@ define void @test_int_x86_aor64(ptr %A, i64 %B) {
 ; X64:       # %bb.0:
 ; X64-NEXT:    aorq %rsi, (%rdi) # encoding: [0xf2,0x48,0x0f,0x38,0xfc,0x37]
 ; X64-NEXT:    retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_aor64:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    aorq %rsi, (%rdi) # EVEX TO LEGACY Compression encoding: [0xf2,0x48,0x0f,0x38,0xfc,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   call void @llvm.x86.aor64(ptr %A, i64 %B)
   ret  void
 }
@@ -36,6 +52,11 @@ define void @test_int_x86_axor64(ptr %A, i64 %B) {
 ; X64:       # %bb.0:
 ; X64-NEXT:    axorq %rsi, (%rdi) # encoding: [0xf3,0x48,0x0f,0x38,0xfc,0x37]
 ; X64-NEXT:    retq # encoding: [0xc3]
+;
+; EGPR-LABEL: test_int_x86_axor64:
+; EGPR:       # %bb.0:
+; EGPR-NEXT:    axorq %rsi, (%rdi) # EVEX TO LEGACY Compression encoding: [0xf3,0x48,0x0f,0x38,0xfc,0x37]
+; EGPR-NEXT:    retq # encoding: [0xc3]
   call void @llvm.x86.axor64(ptr %A, i64 %B)
   ret  void
 }
diff --git a/llvm/test/MC/Disassembler/X86/apx/movbe.txt b/llvm/test/MC/Disassembler/X86/apx/movbe.txt
new file mode 100644
index 00000000000000..716bd169a02221
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/movbe.txt
@@ -0,0 +1,86 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   movbew	%dx, %ax
+# INTEL: movbe	ax, dx
+0x62,0xf4,0x7d,0x08,0x61,0xd0
+
+# ATT:   movbew	%dx, 123(%rax,%rbx,4)
+# INTEL: movbe	word ptr [rax + 4*rbx + 123], dx
+0x62,0xf4,0x7d,0x08,0x61,0x54,0x98,0x7b
+
+# ATT:   movbel	%ecx, %edx
+# INTEL: movbe	edx, ecx
+0x62,0xf4,0x7c,0x08,0x61,0xca
+
+# ATT:   movbel	%ecx, 123(%rax,%rbx,4)
+# INTEL: movbe	dword ptr [rax + 4*rbx + 123], ecx
+0x62,0xf4,0x7c,0x08,0x61,0x4c,0x98,0x7b
+
+# ATT:   movbeq	%r9, %r15
+# INTEL: movbe	r15, r9
+0x62,0x54,0xfc,0x08,0x61,0xcf
+
+# ATT:   movbeq	%r9, 123(%rax,%rbx,4)
+# INTEL: movbe	qword ptr [rax + 4*rbx + 123], r9
+0x62,0x74,0xfc,0x08,0x61,0x4c,0x98,0x7b
+
+# ATT:   movbew	123(%rax,%rbx,4), %dx
+# INTEL: movbe	dx, word ptr [rax + 4*rbx + 123]
+0x62,0xf4,0x7d,0x08,0x60,0x54,0x98,0x7b
+
+# ATT:   movbel	123(%rax,%rbx,4), %ecx
+# INTEL: movbe	ecx, dword ptr [rax + 4*rbx + 123]
+0x62,0xf4,0x7c,0x08,0x60,0x4c,0x98,0x7b
+
+# ATT:   movbeq	123(%rax,%rbx,4), %r9
+# INTEL: movbe	r9, qword ptr [rax + 4*rbx + 123]
+0x62,0x74,0xfc,0x08,0x60,0x4c,0x98,0x7b
+
+# ATT:   movbew	%r17w, %r21w
+# INTEL: movbe	r21w, r17w
+0x62,0xec,0x7d,0x08,0x61,0xcd
+
+# ATT:   movbew	%r17w, 291(%r28,%r29,4)
+# INTEL: movbe	word ptr [r28 + 4*r29 + 291], r17w
+0x62,0x8c,0x79,0x08,0x61,0x8c,0xac,0x23,0x01,0x00,0x00
+
+# ATT:   movbel	%r18d, %r22d
+# INTEL: movbe	r22d, r18d
+0x62,0xec,0x7c,0x08,0x61,0xd6
+
+# ATT:   movbel	%r18d, 291(%r28,%r29,4)
+# INTEL: movbe	dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8c,0x78,0x08,0x61,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT:   movbeq	%r19, %r23
+# INTEL: movbe	r23, r19
+0x62,0xec,0xfc,0x08,0x61,0xdf
+
+# ATT:   movbeq	%r19, 291(%r28,%r29,4)
+# INTEL: movbe	qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8c,0xf8,0x08,0x61,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT:   movbew	291(%r28,%r29,4), %r17w
+# INTEL: movbe	r17w, word ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x79,0x08,0x60,0x8c,0xac,0x23,0x01,0x00,0x00
+
+# ATT:   movbel	291(%r28,%r29,4), %r18d
+# INTEL: movbe	r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x78,0x08,0x60,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT:   movbeq	291(%r28,%r29,4), %r19
+# INTEL: movbe	r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf8,0x08,0x60,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT:   movbew	 %r16w, %r17w
+# INTEL: movbe	r17w, r16w
+0x62,0xec,0x7d,0x08,0x60,0xc8
+
+# ATT:   movbel	 %r16d, %r17d
+# INTEL: movbe	r17d, r16d
+0x62,0xec,0x7c,0x08,0x60,0xc8
+
+# ATT:   movbeq	 %r16, %r17
+# INTEL: movbe	r17, r16
+0x62,0xec,0xfc,0x08,0x60,0xc8
diff --git a/llvm/test/MC/Disassembler/X86/apx/rao-int.txt b/llvm/test/MC/Disassembler/X86/apx/rao-int.txt
new file mode 100644
index 00000000000000..5db6c4b6082588
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/rao-int.txt
@@ -0,0 +1,74 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=...
[truncated]

KanRobert

Need to add pattern for MOVBErr_EVEX, which has the same sematic as "NDD BSWAP"

llvm/lib/Target/X86/X86InstrMisc.td

llvm/lib/Target/X86/X86InstrRAOINT.td

llvm/test/TableGen/x86-fold-tables.inc

llvm/lib/Target/X86/X86InstrMisc.td

llvm/lib/Target/X86/X86InstrRAOINT.td

llvm/lib/Target/X86/X86InstrMisc.td

llvm/lib/Target/X86/X86InstrRAOINT.td

llvm/lib/Target/X86/X86InstrMisc.td

KanRobert

LGTM

XinWang10 requested review from KanRobert and phoebewang and removed request for KanRobert January 9, 2024 09:38

llvmbot added backend:X86 mc Machine (object) code labels Jan 9, 2024

XinWang10 requested a review from RKSimon January 9, 2024 09:42

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RKSimon changed the title ~~[X86] Surpport APX promoted RAO-INT and MOVBE instructions~~ [X86] Support APX promoted RAO-INT and MOVBE instructions Jan 16, 2024

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KanRobert marked this pull request as draft January 18, 2024 16:30

XinWang10 force-pushed the APXRAOINT branch from 97e0df5 to 7b031f5 Compare January 19, 2024 08:20

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XinWang10 added 8 commits January 24, 2024 19:14

[X86] Surpport APX promoted RAO-INT and MOVBE instructions

2278af0

add pattern to movberr

0919f4d

update predicates

ba05382

resolve comment

799d4d1

resolve comment

74f97e8

rewrite with ITy

3c6cb40

update test

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resolve comments

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XinWang10 added 2 commits January 24, 2024 19:14

rewrite raoint multi class

2f4b607

support movberr to bswap

9d0b8cb

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resolve comments

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XinWang10 force-pushed the APXRAOINT branch from aba4644 to a881b3c Compare January 25, 2024 07:04

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XinWang10 added 3 commits January 25, 2024 02:15

add test for ndd,-movbe

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reorder

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use BinOpMR_M

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XinWang10 merged commit 02d5680 into llvm:main Jan 26, 2024

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[X86] Support EVEX compression from MOVBErr to BSWAP #79775

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[X86] Support APX promoted RAO-INT and MOVBE instructions #77431

[X86] Support APX promoted RAO-INT and MOVBE instructions #77431

XinWang10 commented Jan 9, 2024 •

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[X86] Support APX promoted RAO-INT and MOVBE instructions #77431

[X86] Support APX promoted RAO-INT and MOVBE instructions #77431

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