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[AMDGPU] Clean up functions for checking inline literals #81282

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Merged
merged 1 commit into from
Feb 15, 2024
Merged

[AMDGPU] Clean up functions for checking inline literals #81282

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -327,7 +327,7 @@ bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N) const {
return TII->isInlineConstant(C->getAPIntValue());

if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N))
return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt());
return TII->isInlineConstant(C->getValueAPF());

return false;
}
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13 changes: 3 additions & 10 deletions llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
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Expand Up @@ -105,18 +105,11 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {

private:
std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const;
bool isInlineImmediate(const SDNode *N) const;

bool isInlineImmediate16(int64_t Imm) const {
return AMDGPU::isInlinableLiteral16(Imm, Subtarget->hasInv2PiInlineImm());
}

bool isInlineImmediate32(int64_t Imm) const {
return AMDGPU::isInlinableLiteral32(Imm, Subtarget->hasInv2PiInlineImm());
}
bool isInlineImmediate(const SDNode *N) const;

bool isInlineImmediate64(int64_t Imm) const {
return AMDGPU::isInlinableLiteral64(Imm, Subtarget->hasInv2PiInlineImm());
bool isInlineImmediate(const APInt &Imm) const {
return Subtarget->getInstrInfo()->isInlineConstant(Imm);
}

bool isInlineImmediate(const APFloat &Imm) const {
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14 changes: 3 additions & 11 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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Expand Up @@ -4106,7 +4106,7 @@ InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectWMMAVISrc(MachineOperand &Root) const {
std::optional<FPValueAndVReg> FPValReg;
if (mi_match(Root.getReg(), *MRI, m_GFCstOrSplat(FPValReg))) {
if (TII.isInlineConstant(FPValReg->Value.bitcastToAPInt())) {
if (TII.isInlineConstant(FPValReg->Value)) {
return {{[=](MachineInstrBuilder &MIB) {
MIB.addImm(FPValReg->Value.bitcastToAPInt().getSExtValue());
}}};
Expand Down Expand Up @@ -5746,16 +5746,8 @@ void AMDGPUInstructionSelector::renderFPPow2ToExponent(MachineInstrBuilder &MIB,
MIB.addImm(ExpVal);
}

bool AMDGPUInstructionSelector::isInlineImmediate16(int64_t Imm) const {
return AMDGPU::isInlinableLiteral16(Imm, STI.hasInv2PiInlineImm());
}

bool AMDGPUInstructionSelector::isInlineImmediate32(int64_t Imm) const {
return AMDGPU::isInlinableLiteral32(Imm, STI.hasInv2PiInlineImm());
}

bool AMDGPUInstructionSelector::isInlineImmediate64(int64_t Imm) const {
return AMDGPU::isInlinableLiteral64(Imm, STI.hasInv2PiInlineImm());
bool AMDGPUInstructionSelector::isInlineImmediate(const APInt &Imm) const {
return TII.isInlineConstant(Imm);
}

bool AMDGPUInstructionSelector::isInlineImmediate(const APFloat &Imm) const {
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4 changes: 1 addition & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
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Expand Up @@ -353,9 +353,7 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;

bool isInlineImmediate16(int64_t Imm) const;
bool isInlineImmediate32(int64_t Imm) const;
bool isInlineImmediate64(int64_t Imm) const;
bool isInlineImmediate(const APInt &Imm) const;
bool isInlineImmediate(const APFloat &Imm) const;

// Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
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6 changes: 2 additions & 4 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -12965,10 +12965,8 @@ SDValue SITargetLowering::performFPMed3ImmCombine(SelectionDAG &DAG,

const SIInstrInfo *TII = getSubtarget()->getInstrInfo();

if ((!K0->hasOneUse() ||
TII->isInlineConstant(K0->getValueAPF().bitcastToAPInt())) &&
(!K1->hasOneUse() ||
TII->isInlineConstant(K1->getValueAPF().bitcastToAPInt()))) {
if ((!K0->hasOneUse() || TII->isInlineConstant(K0->getValueAPF())) &&
(!K1->hasOneUse() || TII->isInlineConstant(K1->getValueAPF()))) {
return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0),
Var, SDValue(K0, 0), SDValue(K1, 0));
}
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12 changes: 2 additions & 10 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Expand Up @@ -797,16 +797,8 @@ def i64imm_32bit : ImmLeaf<i64, [{
return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
}]>;

def InlineImm16 : ImmLeaf<i16, [{
return isInlineImmediate16(Imm);
}]>;

def InlineImm32 : ImmLeaf<i32, [{
return isInlineImmediate32(Imm);
}]>;

def InlineImm64 : ImmLeaf<i64, [{
return isInlineImmediate64(Imm);
def InlineImm64 : IntImmLeaf<i64, [{
return isInlineImmediate(Imm);
}]>;

def InlineImmFP32 : FPImmLeaf<f32, [{
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