[AMDGPU][GlobalISel] Allow bitcast of bf16

[shiltian]

This is a prime patch for #80908. This change doesn't break anything, though we can't test that much, given what mentioned in https://github.com/llvm/llvm-project/pull/80908/files#r1483394728.

[llvmbot]

@llvm/pr-subscribers-llvm-globalisel

Author: Shilei Tian (shiltian)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/81674.diff

1 Files Affected:

• (modified) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (+3-2)

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 311dd9d9739a6d..3290262816ef0a 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1562,8 +1562,9 @@ bool IRTranslator::translateBitCast(const User &U,
 
 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
                                  MachineIRBuilder &MIRBuilder) {
-  if (U.getType()->getScalarType()->isBFloatTy() ||
-      U.getOperand(0)->getType()->getScalarType()->isBFloatTy())
+  if (Opcode != TargetOpcode::G_BITCAST &&
+      (U.getType()->getScalarType()->isBFloatTy() ||
+       U.getOperand(0)->getType()->getScalarType()->isBFloatTy()))
     return false;
   Register Op = getOrCreateVReg(*U.getOperand(0));
   Register Res = getOrCreateVReg(U);

[rampitec]

It is there for a reason. You cannot really enable it without implementing global isel support for bf16. It will start failing silently. The point of this code to fail with an error. It will also start silently failing for multiple targets.

[shiltian]

It is there for a reason. You cannot really enable it without implementing global isel support for bf16. It will start failing silently. The point of this code to fail with an error. It will also start silently failing for multiple targets.

Okay. Then I'll disable the test in #80908 since it is not supported yet.

[arsenm]

It is there for a reason. You cannot really enable it without implementing global isel support for bf16. It will start failing silently. The point of this code to fail with an error. It will also start silently failing for multiple targets.

You can, bitcast doesn't count as a bfloat operation. As long as we fail on all the actual bfloat operations, it's OK.

[jurahul]

@arsenm @shiltian It seems this change was deemed OK but never committed? Wondering if its OK to resurrect it?

[arsenm]

It would require a bunch more work to guarantee bfloat fallbacks. We miss them in a variety of contexts. I think effort would be better spent just adding bfloat support

[jurahul]

I mean specifically for G_BITCAST, where the type is immaterial

[jurahul]

Also, looks like there is some thinking of adding bf16 as a LLT, but the comment at the top of LowLevetType.h says:

/// Other information required for correct selection is expected to be carried
/// by the opcode, or non-type flags. For example the distinction between G_ADD
/// and G_FADD for int/float or fast-math flags.

Does that mean adding bf16 support means adding new fields to GMIR classes like G_FADD instead to carry the type?

[jurahul]

Nvm, I found this: https://discourse.llvm.org/t/rfc-globalisel-encoding-type-information-into-fp-operations/75107/1 and reading through it now