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[RISCV] Change how MMO is rebuilt in lowerFixedLengthVectorLoadToRVV/lowerFixedLengthVectorStoreToRVV #88811

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Merged
topperc merged 1 commit into from
Apr 16, 2024
Merged

[RISCV] Change how MMO is rebuilt in lowerFixedLengthVectorLoadToRVV/lowerFixedLengthVectorStoreToRVV #88811

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19 changes: 5 additions & 14 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10403,14 +10403,10 @@ RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
if (MinVLMAX == MaxVLMAX && MinVLMAX == VT.getVectorNumElements() &&
getLMUL1VT(ContainerVT).bitsLE(ContainerVT)) {
MachineMemOperand *MMO = Load->getMemOperand();
MachineFunction &MF = DAG.getMachineFunction();
MMO = MF.getMachineMemOperand(
MMO, MMO->getPointerInfo(),
MMO->getMemoryType().isValid()
? LLT::scalable_vector(1, MMO->getMemoryType().getSizeInBits())
: MMO->getMemoryType());
SDValue NewLoad =
DAG.getLoad(ContainerVT, DL, Load->getChain(), Load->getBasePtr(), MMO);
DAG.getLoad(ContainerVT, DL, Load->getChain(), Load->getBasePtr(),
MMO->getPointerInfo(), MMO->getBaseAlign(), MMO->getFlags(),
MMO->getAAInfo(), MMO->getRanges());
SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget);
return DAG.getMergeValues({Result, NewLoad.getValue(1)}, DL);
}
Expand Down Expand Up @@ -10470,14 +10466,9 @@ RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
if (MinVLMAX == MaxVLMAX && MinVLMAX == VT.getVectorNumElements() &&
getLMUL1VT(ContainerVT).bitsLE(ContainerVT)) {
MachineMemOperand *MMO = Store->getMemOperand();
MachineFunction &MF = DAG.getMachineFunction();
MMO = MF.getMachineMemOperand(
MMO, MMO->getPointerInfo(),
MMO->getMemoryType().isValid()
? LLT::scalable_vector(1, MMO->getMemoryType().getSizeInBits())
: MMO->getMemoryType());
return DAG.getStore(Store->getChain(), DL, NewValue, Store->getBasePtr(),
MMO);
MMO->getPointerInfo(), MMO->getBaseAlign(),
MMO->getFlags(), MMO->getAAInfo());
}

SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
Expand Down
19 changes: 19 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/pr88799.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=riscv64-unknown-linux-gnu -mattr=+v | FileCheck %s

define i32 @main() vscale_range(2,2) {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %vector.body
; CHECK-NEXT: lui a0, 1040368
; CHECK-NEXT: addiw a0, a0, -144
; CHECK-NEXT: vl2re16.v v8, (a0)
; CHECK-NEXT: vs2r.v v8, (zero)
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
vector.body:
%0 = load <16 x i16>, ptr getelementptr ([3 x [23 x [23 x i16]]], ptr null, i64 -10593, i64 1, i64 22, i64 0), align 16
store <16 x i16> %0, ptr null, align 2
%wide.load = load <vscale x 8 x i16>, ptr getelementptr ([3 x [23 x [23 x i16]]], ptr null, i64 -10593, i64 1, i64 22, i64 0), align 16
store <vscale x 8 x i16> %wide.load, ptr null, align 2
ret i32 0
}