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[clang backend] In AArch64's DataLayout, specify a minimum function alignment of 4. #90702

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Merged
merged 6 commits into from
May 6, 2024
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[clang backend] In AArch64's DataLayout, specify a minimum function alignment of 4. #90702

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4c312af
In AArch64's DataLayout, specify a minimum function alignment of 4.
May 1, 2024
5a2b9e1
Move "-Fn32" to the end of the data layout strings, to make the
May 1, 2024
43ca2b2
Fix tests:
May 1, 2024
aec3a3d
AutoUpgrade: don't try to upgrade an empty string.
May 1, 2024
aad17e8
More correct DataLayoutUpgradeTests
May 2, 2024
5002204
Merge branch 'main' into min_sect_align_2
fhahn May 2, 2024
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12 changes: 6 additions & 6 deletions clang/lib/Basic/Targets/AArch64.cpp
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Expand Up @@ -1480,11 +1480,11 @@ AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple,
void AArch64leTargetInfo::setDataLayout() {
if (getTriple().isOSBinFormatMachO()) {
if(getTriple().isArch32Bit())
resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128", "_");
resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128-Fn32", "_");
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Just to double check @TNorthover, is an alignment of 32 OK for arm64_32?

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Yep. CPU would hard-fault if that was violated. All instructions are 4 bytes and must be aligned.

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Is this true even if the cpu was executing thumb2 instructions in AArch32 mode?

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Thumb2 function pointers aren't aligned... but from LLVM's perspective it's a completely different target, so it's not relevant.

else
resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128", "_");
resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128-Fn32", "_");
} else
resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32");
}

void AArch64leTargetInfo::getTargetDefines(const LangOptions &Opts,
Expand All @@ -1507,7 +1507,7 @@ void AArch64beTargetInfo::getTargetDefines(const LangOptions &Opts,

void AArch64beTargetInfo::setDataLayout() {
assert(!getTriple().isOSBinFormatMachO());
resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32");
}

WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple,
Expand All @@ -1530,8 +1530,8 @@ WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple,

void WindowsARM64TargetInfo::setDataLayout() {
resetDataLayout(Triple.isOSBinFormatMachO()
? "e-m:o-i64:64-i128:128-n32:64-S128"
: "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128",
? "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"
: "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128-Fn32",
Triple.isOSBinFormatMachO() ? "_" : "");
}

Expand Down
2 changes: 1 addition & 1 deletion clang/test/CodeGen/aarch64-type-sizes.c
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
// RUN: %clang_cc1 -triple aarch64_be-none-linux-gnu -emit-llvm -w -o - %s | FileCheck %s
// char by definition has size 1

// CHECK: target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
// CHECK: target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"

int check_short(void) {
return sizeof(short);
Expand Down
2 changes: 1 addition & 1 deletion clang/test/CodeGen/coff-aarch64-type-sizes.c
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// RUN: %clang_cc1 -triple aarch64-windows -emit-llvm -w -o - %s | FileCheck %s

// CHECK: target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
// CHECK: target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128-Fn32"
// CHECK: target triple = "aarch64-unknown-windows-msvc"

int check_short(void) {
Expand Down
6 changes: 3 additions & 3 deletions clang/test/CodeGen/target-data.c
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Expand Up @@ -185,15 +185,15 @@

// RUN: %clang_cc1 -triple arm64-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=AARCH64
// AARCH64: target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
// AARCH64: target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"

// RUN: %clang_cc1 -triple arm64_32-apple-ios7.0 -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=AARCH64-ILP32
// AARCH64-ILP32: target datalayout = "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128"
// AARCH64-ILP32: target datalayout = "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128-Fn32"

// RUN: %clang_cc1 -triple arm64-pc-win32-macho -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=AARCH64-WIN32-MACHO
// AARCH64-WIN32-MACHO: target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
// AARCH64-WIN32-MACHO: target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"

// RUN: %clang_cc1 -triple thumb-unknown-gnueabi -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=THUMB
Expand Down
6 changes: 3 additions & 3 deletions clang/test/CodeGenCXX/member-alignment.cpp
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Expand Up @@ -5,11 +5,11 @@
// RUN: %clang_cc1 -emit-llvm -triple ppc64le-unknown-linux-gnu %s -o - | \
// RUN: FileCheck -check-prefix CHECK-NOEXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple arm64-unknown-linux-gnu %s -o - | \
// RUN: FileCheck -check-prefix CHECK-EXTRAALIGN %s
// RUN: FileCheck -check-prefix CHECK-NOEXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple arm64-apple-ios %s -o - | \
// RUN: FileCheck -check-prefix CHECK-EXTRAALIGN %s
// RUN: FileCheck -check-prefix CHECK-NOEXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple aarch64-unknown-linux-gnu %s -o - | \
// RUN: FileCheck -check-prefix CHECK-EXTRAALIGN %s
// RUN: FileCheck -check-prefix CHECK-NOEXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple mips-unknown-linux-gnu %s -o - | \
// RUN: FileCheck -check-prefix CHECK-EXTRAALIGN %s
// RUN: %clang_cc1 -emit-llvm -triple x86_64-unknown-fuchsia %s -o - | \
Expand Down
20 changes: 10 additions & 10 deletions clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp
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Expand Up @@ -2728,7 +2728,7 @@ int main() {
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SC1El
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Expand All @@ -2741,7 +2741,7 @@ int main() {
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1ScvcEv
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] comdat {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand Down Expand Up @@ -3214,7 +3214,7 @@ int main() {
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SD1Ev
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand All @@ -3224,7 +3224,7 @@ int main() {
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SC2El
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Expand All @@ -3238,7 +3238,7 @@ int main() {
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SD2Ev
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand Down Expand Up @@ -3980,7 +3980,7 @@ int main() {
//
//
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SC1El
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Expand All @@ -3993,7 +3993,7 @@ int main() {
//
//
// CHECK13-LABEL: define {{[^@]+}}@_ZN1ScvcEv
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] comdat {
// CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand Down Expand Up @@ -4466,7 +4466,7 @@ int main() {
//
//
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SD1Ev
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand All @@ -4476,7 +4476,7 @@ int main() {
//
//
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SC2El
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 noundef [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Expand Down Expand Up @@ -5093,7 +5093,7 @@ int main() {
//
//
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand Down
30 changes: 15 additions & 15 deletions clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp
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Expand Up @@ -3235,7 +3235,7 @@ int main() {
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SC1El
// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Expand All @@ -3248,7 +3248,7 @@ int main() {
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1ScvcEv
// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {
// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] comdat {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand Down Expand Up @@ -3749,7 +3749,7 @@ int main() {
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SD1Ev
// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand All @@ -3759,7 +3759,7 @@ int main() {
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SC2El
// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Expand All @@ -3773,7 +3773,7 @@ int main() {
//
//
// CHECK9-LABEL: define {{[^@]+}}@_ZN1SD2Ev
// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK9-NEXT: entry:
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand Down Expand Up @@ -4558,7 +4558,7 @@ int main() {
//
//
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SC1El
// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Expand All @@ -4571,7 +4571,7 @@ int main() {
//
//
// CHECK11-LABEL: define {{[^@]+}}@_ZN1ScvcEv
// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {
// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] comdat {
// CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand Down Expand Up @@ -4747,7 +4747,7 @@ int main() {
//
//
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SD1Ev
// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat {
// CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand All @@ -4757,7 +4757,7 @@ int main() {
//
//
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SC2El
// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat {
// CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Expand All @@ -4771,7 +4771,7 @@ int main() {
//
//
// CHECK11-LABEL: define {{[^@]+}}@_ZN1SD2Ev
// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 {
// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat {
// CHECK11-NEXT: entry:
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand Down Expand Up @@ -4910,7 +4910,7 @@ int main() {
//
//
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SC1El
// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
// CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Expand All @@ -4923,7 +4923,7 @@ int main() {
//
//
// CHECK13-LABEL: define {{[^@]+}}@_ZN1ScvcEv
// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] comdat align 2 {
// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] comdat {
// CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand Down Expand Up @@ -5424,7 +5424,7 @@ int main() {
//
//
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SD1Ev
// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand All @@ -5434,7 +5434,7 @@ int main() {
//
//
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SC2El
// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]], i64 [[A:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Expand Down Expand Up @@ -6107,7 +6107,7 @@ int main() {
//
//
// CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev
// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 {
// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat {
// CHECK13-NEXT: entry:
// CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
// CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/IR/AutoUpgrade.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5406,6 +5406,14 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
return Res;
}

// AArch64 data layout upgrades.
if (T.isAArch64()) {
// Add "-Fn32"
if (!DL.empty() && !DL.contains("-Fn32"))
Res.append("-Fn32");
return Res;
}

if (!T.isX86())
return Res;

Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
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Expand Up @@ -275,15 +275,15 @@ static std::string computeDataLayout(const Triple &TT,
bool LittleEndian) {
if (TT.isOSBinFormatMachO()) {
if (TT.getArch() == Triple::aarch64_32)
return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
return "e-m:o-i64:64-i128:128-n32:64-S128";
return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128-Fn32";
return "e-m:o-i64:64-i128:128-n32:64-S128-Fn32";
}
if (TT.isOSBinFormatCOFF())
return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128-Fn32";
std::string Endian = LittleEndian ? "e" : "E";
std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
return Endian + "-m:e" + Ptr32 +
"-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
"-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32";
}

static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
Expand Down
9 changes: 6 additions & 3 deletions llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,8 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) {
"e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32", "i686-pc-windows-msvc");
std::string DL3 = UpgradeDataLayoutString(
"e-m:o-i64:64-f80:128-n8:16:32:64-S128", "x86_64-apple-macosx");
std::string DL4 =
UpgradeDataLayoutString("e-m:o-i64:64-i128:128-n32:64-S128", "aarch64--");
EXPECT_EQ(DL1,
"e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128"
"-f80:128-n8:16:32:64-S128");
Expand All @@ -29,6 +31,7 @@ TEST(DataLayoutUpgradeTest, ValidDataLayoutUpgrade) {
"-f80:128-n8:16:32-S32");
EXPECT_EQ(DL3, "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:"
"128-n8:16:32:64-S128");
EXPECT_EQ(DL4, "e-m:o-i64:64-i128:128-n32:64-S128-Fn32");

// Check that AMDGPU targets add -G1 if it's not present.
EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32", "r600"), "e-p:32:32-G1");
Expand Down Expand Up @@ -78,15 +81,15 @@ TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) {
"x86_64-unknown-linux-gnu");
std::string DL2 = UpgradeDataLayoutString("e-m:e-i64:64-n32:64",
"powerpc64le-unknown-linux-gnu");
std::string DL3 =
UpgradeDataLayoutString("e-m:o-i64:64-i128:128-n32:64-S128", "aarch64--");
std::string DL3 = UpgradeDataLayoutString(
"e-m:o-i64:64-i128:128-n32:64-S128-Fn32", "aarch64--");
EXPECT_EQ(
DL1,
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-i128:128:128"
"-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64"
"-f80:128:128-n8:16:32:64-S128");
EXPECT_EQ(DL2, "e-m:e-i64:64-n32:64");
EXPECT_EQ(DL3, "e-m:o-i64:64-i128:128-n32:64-S128");
EXPECT_EQ(DL3, "e-m:o-i64:64-i128:128-n32:64-S128-Fn32");

// Check that AMDGPU targets don't add -G1 if there is already a -G flag.
EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32-G2", "r600"), "e-p:32:32-G2");
Expand Down
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