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[AMDGPU] Extend llvm.amdgcn.update.dpp intrinsic to support f64 #91190

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Merged
merged 4 commits into from
May 13, 2024
Merged

[AMDGPU] Extend llvm.amdgcn.update.dpp intrinsic to support f64 #91190

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18c9f96
[AMDGPU] Extend llvm.amdgcn.update.dpp intrinsic to support f64
vikramRH May 6, 2024
e98b704
use foreach instead of new class
vikramRH May 7, 2024
57851b7
review comments, added tests for ptr, float2 and v2i32
vikramRH May 7, 2024
ceae543
added 32 bit pointer tests
vikramRH May 8, 2024
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4 changes: 3 additions & 1 deletion llvm/lib/Target/AMDGPU/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3338,13 +3338,15 @@ def : GCNPat <
(as_i1timm $bound_ctrl))
>;

foreach vt = Reg64Types.types in {
def : GCNPat <
(i64 (int_amdgcn_update_dpp i64:$old, i64:$src, timm:$dpp_ctrl, timm:$row_mask,
(vt (int_amdgcn_update_dpp vt:$old, vt:$src, timm:$dpp_ctrl, timm:$row_mask,
timm:$bank_mask, timm:$bound_ctrl)),
(V_MOV_B64_DPP_PSEUDO VReg_64_Align2:$old, VReg_64_Align2:$src, (as_i32timm $dpp_ctrl),
(as_i32timm $row_mask), (as_i32timm $bank_mask),
(as_i1timm $bound_ctrl))
>;
}

//===----------------------------------------------------------------------===//
// Fract Patterns
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.td
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Expand Up @@ -586,6 +586,7 @@ class RegisterTypes<list<ValueType> reg_types> {

def Reg16Types : RegisterTypes<[i16, f16, bf16]>;
def Reg32Types : RegisterTypes<[i32, f32, v2i16, v2f16, v2bf16, p2, p3, p5, p6]>;
def Reg64Types : RegisterTypes<[i64, f64, v2i32, v2f32, p0]>;
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We'll need to do something about other address spaces for globalisel, eventually


let HasVGPR = 1 in {
// VOP3 and VINTERP can access 256 lo and 256 hi registers.
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9 changes: 3 additions & 6 deletions llvm/lib/Target/AMDGPU/VOP1Instructions.td
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Expand Up @@ -1340,19 +1340,16 @@ def : GCNPat <
(as_i1timm $bound_ctrl))
>;

class UpdateDPPPat<ValueType vt> : GCNPat <
foreach vt = Reg32Types.types in {
def : GCNPat <
(vt (int_amdgcn_update_dpp vt:$old, vt:$src, timm:$dpp_ctrl,
timm:$row_mask, timm:$bank_mask,
timm:$bound_ctrl)),
(V_MOV_B32_dpp VGPR_32:$old, VGPR_32:$src, (as_i32timm $dpp_ctrl),
(as_i32timm $row_mask), (as_i32timm $bank_mask),
(as_i1timm $bound_ctrl))
>;

def : UpdateDPPPat<i32>;
def : UpdateDPPPat<f32>;
def : UpdateDPPPat<v2i16>;
def : UpdateDPPPat<v2f16>;
}

} // End OtherPredicates = [isGFX8Plus]

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