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[Exegesis] Changing non-standard CHECK in tests to more compliant way #93222

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Merged
merged 1 commit into from
May 29, 2024
Merged

[Exegesis] Changing non-standard CHECK in tests to more compliant way #93222

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2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/AArch64/latency-by-opcode-name.s
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Original file line number Diff line number Diff line change
Expand Up @@ -10,4 +10,4 @@ CHECK-NEXT: config: ''
CHECK-NEXT: register_initial_values:
CHECK-DAG: - '[[REG2]]=0x0'
# We don't check REG3 because in the case that REG2=REG3 the check would fail
CHECK-LAST: ...
CHECK-DAG: ...
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/Mips/latency-GPR64.s
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Expand Up @@ -9,4 +9,4 @@ CHECK-NEXT: AND64
CHECK-NEXT: config: ''
CHECK-NEXT: register_initial_values:
CHECK-DAG: - '[[REG1:[A-Z0-9]+_64]]=0x0'
CHECK-LAST: ...
CHECK-DAG: ...
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/Mips/latency-by-opcode-name.s
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Expand Up @@ -9,4 +9,4 @@ CHECK-NEXT: ADD
CHECK-NEXT: config: ''
CHECK-NEXT: register_initial_values:
CHECK-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
CHECK-LAST: ...
CHECK-DAG: ...
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/PowerPC/latency-by-opcode-name.s
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Expand Up @@ -8,4 +8,4 @@ CHECK-NEXT: ADD8
CHECK-NEXT: config: ''
CHECK-NEXT: register_initial_values:
CHECK-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
CHECK-LAST: ...
CHECK-DAG: ...
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/X86/latency/latency-CMOV32rr.s
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Expand Up @@ -8,4 +8,4 @@ CHECK-NEXT: key:
CHECK-NEXT: instructions:
CHECK-NEXT: 'CMOV32rr {{.*}} i_0x{{[0-9a-f]}}'
CHECK-NEXT: config: ''
CHECK-LAST: ...
CHECK-DAG: ...
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/X86/latency/latency-IN16rr.s
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Expand Up @@ -12,4 +12,4 @@ CHECK-NEXT: - {{.*}}
CHECK-NEXT: config: ''
CHECK-NEXT: register_initial_values:
CHECK-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
CHECK-LAST: ...
CHECK-DAG: ...
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/X86/latency/latency-SBB8rr.s
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Expand Up @@ -9,4 +9,4 @@ CHECK-NEXT: SBB8rr
CHECK-NEXT: config: ''
CHECK-NEXT: register_initial_values:
CHECK-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
CHECK-LAST: ...
CHECK-DAG: ...
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/X86/latency/latency-SQRTSSr.s
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Expand Up @@ -10,4 +10,4 @@ CHECK-NEXT: SQRTSSr
CHECK-NEXT: config: ''
CHECK-NEXT: register_initial_values:
CHECK-NOT: crashed
CHECK-LAST: ...
CHECK-DAG: ...
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/X86/latency/latency-by-opcode-name.s
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Expand Up @@ -9,4 +9,4 @@ CHECK-NEXT: ADD32rr
CHECK-NEXT: config: ''
CHECK-NEXT: register_initial_values:
CHECK-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
CHECK-LAST: ...
CHECK-DAG: ...
4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-exegesis/X86/latency/max-configs.test
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Expand Up @@ -9,7 +9,7 @@ CHECK-NEXT: SBB8rr
CHECK-NEXT: config: ''
CHECK-NEXT: register_initial_values:
CHECK-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
CHECK-LAST: ...
CHECK-DAG: ...

CHECK1-NOT: SBB8rr

Expand All @@ -21,4 +21,4 @@ CHECK2-NEXT: SBB8rr
CHECK2-NEXT: config: ''
CHECK2-NEXT: register_initial_values:
CHECK2-DAG: - '[[REG1:[A-Z0-9]+]]=0x0'
CHECK2-LAST: ...
CHECK2-DAG: ...
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/X86/lbr/mov-add.s
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Expand Up @@ -16,4 +16,4 @@ CHECK-NEXT: {{.*}}
CHECK-NEXT: num_repetitions: 10000
CHECK-NEXT: measurements:
CHECK-NEXT: {{.*}} value: 0.0001, per_snippet_value: 0.0002 {{.*}}
CHECK-LAST: ...
CHECK-DAG: ...
2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-exegesis/X86/uops/uops-CMOV16rm-noreg-serialization.s
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Expand Up @@ -8,4 +8,4 @@ CHECK-YAML-NEXT: mode: uops
CHECK-YAML-NEXT: key:
CHECK-YAML-NEXT: instructions:
CHECK-YAML-NEXT: - 'CMOV16rm {{[A-Z0-9]+}} {{[A-Z0-9]+}} {{[A-Z0-9]+}} i_0x1 %noreg i_0x0 %noreg i_0x{{[0-9a-f]}}'
CHECK-YAML-LAST: ...
CHECK-YAML-DAG: ...
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