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[CodeGen] Guard copy propagation in machine CSE against undefs #97413

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Merged
vikramRH merged 4 commits into from
Jul 12, 2024
Merged

[CodeGen] Guard copy propagation in machine CSE against undefs #97413

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[CodeGen][NFC] Guard copy propogation in machine CSE against undefs
vikramRH Jul 2, 2024
83d1658
add test
vikramRH Jul 4, 2024
5832062
review comments
vikramRH Jul 8, 2024
08bdad3
review comment
vikramRH Jul 11, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/MachineCSE.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,7 @@ bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
continue;
bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
MachineInstr *DefMI = MRI->getVRegDef(Reg);
if (!DefMI->isCopy())
if (!DefMI || !DefMI->isCopy())
continue;
Register SrcReg = DefMI->getOperand(1).getReg();
if (!SrcReg.isVirtual())
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22 changes: 22 additions & 0 deletions llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
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@@ -0,0 +1,22 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -run-pass=machine-cse -verify-machineinstrs -o - %s | FileCheck %s

# Test to ensure that this does not crash on undefs
---
name: copyprop_regsequence_with_undef
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: copyprop_regsequence_with_undef
; CHECK: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %3:sreg_32, %subreg.sub0, [[DEF]], %subreg.sub1
; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %5:sreg_32, %subreg.sub0, [[DEF1]], %subreg.sub1
; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[REG_SEQUENCE]].sub1, [[REG_SEQUENCE1]].sub1, implicit-def $scc
%0:sreg_32 = IMPLICIT_DEF
%1:sreg_32 = IMPLICIT_DEF
%4:sreg_64 = REG_SEQUENCE undef %10:sreg_32, %subreg.sub0, %0:sreg_32, %subreg.sub1
%5:sreg_64 = REG_SEQUENCE undef %11:sreg_32, %subreg.sub0, %1:sreg_32, %subreg.sub1
%6:sreg_32 = S_ADD_I32 %4.sub1:sreg_64, %5.sub1:sreg_64, implicit-def $scc

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