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[AArch64] All bits of an exact right shift are demanded #97448

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Merged
merged 2 commits into from
Jul 5, 2024
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[AArch64] All bits of an exact right shift are demanded #97448

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[AArch64] All bits of an exact right shift are demanded
momchil-velikov Jul 2, 2024
647c4c1
[fixup] Do the same for logical shift right too
momchil-velikov Jul 3, 2024
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4 changes: 4 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -22142,6 +22142,10 @@ static SDValue performVectorShiftCombine(SDNode *N,
if (DCI.DAG.ComputeNumSignBits(Op.getOperand(0)) > ShiftImm)
return Op.getOperand(0);

// If the shift is exact, the shifted out bits matter.
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nit: perhaps elaborate a bit on why the shifted out bits matter. E.g. "because we may fold the right shift with other instructions and thus require the lower bits to be set."

Now that gets me thinking. Wouldn't this condition than make code that does not fold the right shift with other instructions less efficient? Shouldn't the onus be on wherever folds right shift with sitofp (scvtf) to make sure to clear the lower bits?

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(Somehow didn't send this out before -- posting for posterity.)

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I wrote that in the commit message

However, these elements need to stay zero if the right shift is exact, or otherwise we will be introducing undefined behavior.

if (N->getFlags().hasExact())
return SDValue();

APInt ShiftedOutBits = APInt::getLowBitsSet(OpScalarSize, ShiftImm);
APInt DemandedMask = ~ShiftedOutBits;

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35 changes: 35 additions & 0 deletions llvm/test/CodeGen/AArch64/shr-exact-demanded-bits.ll
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@@ -0,0 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s | FileCheck %s
target triple = "aarch64-linux"

define <2 x i32> @f(i8 %0, i8 %1) {
; CHECK-LABEL: f:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.b[3], w0
; CHECK-NEXT: mov v0.b[7], w1
; CHECK-NEXT: sshr v0.2s, v0.2s, #24
; CHECK-NEXT: ret
%3 = insertelement <2 x i8> poison, i8 %0, i64 0
%4 = insertelement <2 x i8> %3, i8 %1, i64 1
%5 = shufflevector <2 x i8> %4, <2 x i8> <i8 0, i8 poison>, <8 x i32> <i32 2, i32 2, i32 2, i32 0, i32 2, i32 2, i32 2, i32 1>
%6 = bitcast <8 x i8> %5 to <2 x i32>
%7 = ashr exact <2 x i32> %6, <i32 24, i32 24>
ret <2 x i32> %7
}

define <2 x i32> @g(i8 %0, i8 %1) {
; CHECK-LABEL: g:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.b[3], w0
; CHECK-NEXT: mov v0.b[7], w1
; CHECK-NEXT: ushr v0.2s, v0.2s, #24
; CHECK-NEXT: ret
%3 = insertelement <2 x i8> poison, i8 %0, i64 0
%4 = insertelement <2 x i8> %3, i8 %1, i64 1
%5 = shufflevector <2 x i8> %4, <2 x i8> <i8 0, i8 poison>, <8 x i32> <i32 2, i32 2, i32 2, i32 0, i32 2, i32 2, i32 2, i32 1>
%6 = bitcast <8 x i8> %5 to <2 x i32>
%7 = lshr exact <2 x i32> %6, <i32 24, i32 24>
ret <2 x i32> %7
}
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