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Add support for verilog/vhdl files with custom file endings #207
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Replaces assumptions proposed in #194. |
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LGTM! The only suggestion I have is that the new keys sv
, v
and vhd
could be nested instead of being equal to files
. For instance, something like this would make a bit more sense to me:
sources:
# Individual source files are simple string entries:
- src/package.sv
- src/file1.vhd
- src/file2.vhd
# Source files can be grouped:
- files:
- src/stuff/pkg.sv
- src/stuff/top.sv
- sv: vendor/encrypted_sv_src.svp
- v: vendor/encrypted_v_src.vp
- vhd: vendor/encrypted_vhd_src.e
// /// A SystemVerilog file. | ||
// SystemVerilog, |
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Can be removed?
This should already be supported. The sv/v/vhd keys can be used in place of a sourcefile (or a sourcegroup), so even within sourcegroups we can use these keys. These sourcegroups and sourcefiles can be nested hierarchically as desired. Let me know if this doesn't work for you, or do you want to exclude the option of providing a format-specific file at the top hierarchy? |
Ah no that's already enough. I think I got the impression from the code that |
This PR adds support for custom file endings of vhdl, verilog, or systemverilog files. This is relevant for scripts generated directly for custom tools, e.g., to import encrypted files that have endings such as
.svp
,.vp
, or.e
(or anything else you could think of). Custom file endings can now be allocated a file type as follows: