Deselect ruff-covered pylint rules (#7424)

And clean up associated pylint directives in the code.

No change in the effective code.

Partially implements #7371

Author: pavoljuhas

CONTRIBUTING.md

@@ -137,8 +137,8 @@ constructs. We use [Pylint](https://www.pylint.org/) to check for code lint.
 To see which lint checks we enforce, see the
 [dev_tools/conf/.pylintrc](dev_tools/conf/.pylintrc) file. When Pylint produces
 a false positive, it can be silenced with annotations. For example, the
-annotation `# pylint: disable=unused-import` would silence a warning about
-an unused import.
+annotation `# pylint: disable=wrong-import-order` would silence a warning about
+wrong import order.
 
 ### Types
 

cirq-core/cirq/__init__.py

@@ -123,7 +123,6 @@
 )
 
 from cirq.linalg import (
-    # pylint: disable=line-too-long
     all_near_zero as all_near_zero,
     all_near_zero_mod as all_near_zero_mod,
     allclose_up_to_global_phase as allclose_up_to_global_phase,
@@ -344,7 +343,6 @@
 
 
 from cirq.transformers import (
-    # pylint: disable=line-too-long
     AbstractInitialMapper as AbstractInitialMapper,
     add_dynamical_decoupling as add_dynamical_decoupling,
     align_left as align_left,
@@ -572,7 +570,6 @@
     ProductState as ProductState,
 )
 
-# pylint: disable=redefined-builtin
 from cirq.protocols import (
     act_on as act_on,
     apply_channel as apply_channel,
@@ -694,12 +691,10 @@
     ZerosSampler as ZerosSampler,
 )
 
-# pylint: enable=redefined-builtin
 
 # Unflattened sub-modules.
 
 # Registers cirq-core's public classes for JSON serialization.
-# pylint: disable=wrong-import-position
 from cirq.protocols.json_serialization import _register_resolver
 from cirq.json_resolver_cache import _class_resolver_dictionary
 
@@ -709,5 +704,3 @@
 # contrib's json resolver cache depends on cirq.DEFAULT_RESOLVER
 
 from cirq import contrib  # noqa: E402
-
-# pylint: enable=wrong-import-position

cirq-core/cirq/_compat_test.py

@@ -394,13 +394,11 @@ class OldClass(NewClass):
         OldClass('1')
 
     with pytest.raises(AssertionError, match='deadline should match vX.Y'):
-        # pylint: disable=unused-variable
+
         @deprecated_class(deadline='invalid', fix='theFix', name='foo')
         class BadlyDeprecatedClass(NewClass):  # pragma: no cover
             ...
 
-        # pylint: enable=unused-variable
-
 
 def _from_parent_import_deprecated():
     from cirq.testing._compat_test_data import fake_a
@@ -566,7 +564,6 @@ def _import_top_level_deprecated():
 def _repeated_import_path():
     """to ensure that the highly unlikely repeated subpath import doesn't interfere"""
 
-    # pylint: disable=line-too-long
     from cirq.testing._compat_test_data.repeated_child.cirq.testing._compat_test_data.repeated_child import (  # type: ignore  # noqa: E501
         child,
     )
@@ -812,7 +809,6 @@ def _test_broken_module_1_inner():
     with pytest.raises(
         DeprecatedModuleImportError, match="missing_module cannot be imported. The typical reasons"
     ):
-        # pylint: disable=unused-import
         import cirq.testing._compat_test_data.broken_ref as br  # type: ignore # noqa: F401
 
 

cirq-core/cirq/contrib/paulistring/clifford_target_gateset.py

@@ -79,7 +79,7 @@ class SingleQubitTarget(Enum):
     def __init__(
         self,
         *,
-        single_qubit_target: SingleQubitTarget = SingleQubitTarget.PAULI_STRING_PHASORS_AND_CLIFFORDS,  # pylint: disable=line-too-long  # noqa: E501
+        single_qubit_target: SingleQubitTarget = SingleQubitTarget.PAULI_STRING_PHASORS_AND_CLIFFORDS,  # noqa: E501
         atol: float = 1e-8,
     ):
         """Initializes CliffordTargetGateset

cirq-core/cirq/experiments/__init__.py

@@ -37,7 +37,6 @@
 )
 
 from cirq.experiments.random_quantum_circuit_generation import (
-    # pylint: disable=line-too-long
     GRID_ALIGNED_PATTERN as GRID_ALIGNED_PATTERN,
     GRID_STAGGERED_PATTERN as GRID_STAGGERED_PATTERN,
     HALF_GRID_STAGGERED_PATTERN as HALF_GRID_STAGGERED_PATTERN,

cirq-core/cirq/json_resolver_cache.py

@@ -237,9 +237,7 @@ def _symmetricalqidpair(qids):
         'VirtualTag': cirq.VirtualTag,
         'WaitGate': cirq.WaitGate,
         # The formatter keeps putting this back
-        # pylint: disable=line-too-long
         'XEBPhasedFSimCharacterizationOptions': cirq.experiments.XEBPhasedFSimCharacterizationOptions,  # noqa: E501
-        # pylint: enable=line-too-long
         '_XEigenState': cirq.value.product_state._XEigenState,
         'XPowGate': cirq.XPowGate,
         'XXPowGate': cirq.XXPowGate,

cirq-core/cirq/linalg/__init__.py

@@ -26,7 +26,6 @@
 )
 
 from cirq.linalg.decompositions import (
-    # pylint: disable=line-too-long
     axis_angle as axis_angle,
     AxisAngleDecomposition as AxisAngleDecomposition,
     deconstruct_single_qubit_matrix_into_angles as deconstruct_single_qubit_matrix_into_angles,
@@ -44,7 +43,6 @@
 )
 
 from cirq.linalg.diagonalize import (
-    # pylint: disable=line-too-long
     bidiagonalize_real_matrix_pair_with_symmetric_products as bidiagonalize_real_matrix_pair_with_symmetric_products,  # noqa: E501
     bidiagonalize_unitary_with_special_orthogonals as bidiagonalize_unitary_with_special_orthogonals,  # noqa: E501
     diagonalize_real_symmetric_and_sorted_diagonal_matrices as diagonalize_real_symmetric_and_sorted_diagonal_matrices,  # noqa: E501

cirq-core/cirq/ops/classically_controlled_operation_test.py

@@ -505,7 +505,6 @@ def test_scope_local() -> None:
     assert internal_control_keys == ['0:0:a', '0:1:a', '1:0:a', '1:1:a']
     assert not cirq.control_keys(outer_subcircuit)
     assert not cirq.control_keys(circuit)
-    # pylint: disable=line-too-long
     cirq.testing.assert_has_diagram(
         cirq.Circuit(outer_subcircuit),
         """
@@ -515,7 +514,6 @@ def test_scope_local() -> None:
 """,  # noqa: E501
         use_unicode_characters=True,
     )
-    # pylint: enable=line-too-long
     cirq.testing.assert_has_diagram(
         circuit,
         """
@@ -659,7 +657,6 @@ def test_scope_extern() -> None:
     assert internal_control_keys == ['0:b', '0:b', '1:b', '1:b']
     assert not cirq.control_keys(outer_subcircuit)
     assert not cirq.control_keys(circuit)
-    # pylint: disable=line-too-long
     cirq.testing.assert_has_diagram(
         cirq.Circuit(outer_subcircuit),
         """
@@ -671,7 +668,6 @@ def test_scope_extern() -> None:
 """,  # noqa: E501
         use_unicode_characters=True,
     )
-    # pylint: enable=line-too-long
     cirq.testing.assert_has_diagram(
         circuit,
         """
@@ -780,7 +776,6 @@ def test_scope_extern_mismatch() -> None:
     assert internal_control_keys == ['b', 'b', 'b', 'b']
     assert cirq.control_keys(outer_subcircuit) == {cirq.MeasurementKey('b')}
     assert cirq.control_keys(circuit) == {cirq.MeasurementKey('b')}
-    # pylint: disable=line-too-long
     cirq.testing.assert_has_diagram(
         cirq.Circuit(outer_subcircuit),
         """
@@ -794,7 +789,6 @@ def test_scope_extern_mismatch() -> None:
 """,  # noqa: E501
         use_unicode_characters=True,
     )
-    # pylint: enable=line-too-long
     cirq.testing.assert_has_diagram(
         circuit,
         """
@@ -984,7 +978,6 @@ def test_sympy_scope() -> None:
         use_unicode_characters=True,
     )
 
-    # pylint: disable=line-too-long
     cirq.testing.assert_has_diagram(
         circuit,
         """
@@ -1000,7 +993,6 @@ def test_sympy_scope() -> None:
 """,  # noqa: E501
         use_unicode_characters=True,
     )
-    # pylint: enable=line-too-long
 
 
 def test_sympy_scope_simulation() -> None:

cirq-core/cirq/ops/clifford_gate_test.py

@@ -125,7 +125,6 @@ def test_init_from_double_invalid(trans1, from1) -> None:
 @pytest.mark.parametrize('trans,frm', itertools.product(_all_rotations(), _paulis))
 def test_init_from_single_map_vs_kwargs(trans, frm) -> None:
     from_str = str(frm).lower() + '_to'
-    # pylint: disable=unexpected-keyword-arg
     gate_kw = cirq.SingleQubitCliffordGate.from_single_map(**{from_str: trans})
     gate_map = cirq.SingleQubitCliffordGate.from_single_map({frm: trans})
     assert gate_kw == gate_map

cirq-core/cirq/ops/fsim_gate_test.py

@@ -490,7 +490,6 @@ def test_phased_fsim_circuit() -> None:
 1: ───PhFSim(0.5π, -π, 0.5π, 0, -0.25π)───PhFSim(-π, 0.5π, 0.1π, 0.2π, 0.3π)───
     """,
     )
-    # pylint: disable=line-too-long
     cirq.testing.assert_has_diagram(
         c,
         """
@@ -510,7 +509,6 @@ def test_phased_fsim_circuit() -> None:
         use_unicode_characters=False,
         precision=None,
     )
-    # pylint: enable=line-too-long
     c = cirq.Circuit(
         cirq.PhasedFSimGate(
             sympy.Symbol('a') + sympy.Symbol('b'),