PCI: read full 64-bit size of 64-bit memory BARs #178
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Can you fix the build failure in the example? Then I'll merge this. |
64-bit memory BARs not only have a 64-bit-wide address, but also a 64-bit-wide size. Change the bar_info() function to retrieve the upper 32 bits of the size and include it in the size calculation. This modifies the return type of the BarInfo::memory_address_size() function, so callers may need to modify their code to adapt to the new 64-bit size. Fixes GitHub issue rcore-os#177.
Reprogramming the BAR address to an all-1s value when attempting to decipher which bits are writable can result in the PCI device actually intercepting memory or I/O accesses to the resulting address. To avoid this, disable the I/O and memory bits in the control register during the BAR sizing process, as recommended by the PCI specification. Fixes GitHub issue rcore-os#176.
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Sorry, the build failure should be fixed now (I thought I tested all the architectures, but I must have skipped aarch64 on the last pass). |
Collaborator
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I think this has introduced a new bug, where unused BARs read as size 0x100000000 rather than size 0. |
Contributor
Author
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Is that for 32-bit or 64-bit BARs? With crosvm, qemu, something else? I will take a look and see if I can reproduce locally - the math is a bit tricky and could probably stand to be simplified anyway. |
Collaborator
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The bug shows up with both crosvm and QEMU. I've added a unit test in #191 which catches the issue. I also noticed a bug where IO BAR sizes less than 16 bytes were read incorrectly, which I fixed. |
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64-bit memory BARs not only have a 64-bit-wide address, but also a 64-bit-wide size. Change the bar_info() function to retrieve the upper 32 bits of the size and include it in the size calculation.
This modifies the return type of the BarInfo::memory_address_size() function, so callers may need to modify their code to adapt to the new 64-bit size.
Fixes GitHub issue #177.