add rationale for which systems are being targetted#813
add rationale for which systems are being targetted#813jackwdandrew wants to merge 2 commits intomasterfrom
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First part contains just basic extensions to establish ACLIC Second part contains microcontroller specific extensions The term microcontroller has precedent in Zce, that declares Zcmp and Zcmt to be extensions tageted to microcontrollers.
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| "Fast" interrupt features have become state of the art in microcontrollers in incumbent architectures. | ||
| Namely, automatic hardware stacking, tailchaining, late arrival, lazy stacking, hardware vectoring, interrupt nesting, and stack pointer swapping. |
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Alexey commented that we can get even smaller memory footprint with software optimized stackframe (e.g. different calling convention).
| These features were introduced to minimize interrupt latency and memory footprint in microcontrollers. | ||
| These are vital in ultra low-cost MCUs fabricated in older process nodes (90nm), running at 10s of MHz with only KiB of memory. | ||
| However, these features become counter-productive as modern microcontrollers move to smaller technology nodes and higher performance, less memory constrained systems. | ||
| It is therefore important to make a distinction between these two types of system, hereafter termed "Low Cost Microcontrollers" and "High Performance Microcontrollers". |
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Christian is trying to align with with the precendent of naming on Zce, where they are explicitly called microcontroller extensions. Very difficult to draw hard lines nowadays.
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Change Low Cost to Resource Constrained.
| For these systems, the cycles and memory saved from fast interrupt features can have a large relative impact on the overall system cost and interrupt latency. | ||
| Therefore, even features that have minimal cycle impact on interrupt latency and only bare metal code could take advantage of are considered for Low Cost Microcontrollers. | ||
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| High Performance Microcontrollers are characterized by high performance (100s of MHz), high memory availability (MiB), newer technology nodes, and running an RTOS or real-time hypervisor. |
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Christian commented that we should take care because RTOS are not mature, so it is not optimized to squeeze out every cycle.
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Alexey commented that we should be sure we can potentially extract benefit in RTOS.
Alexey has some concerns on bare metal applications, he thinks that there are too many custom extensions in hardware that software will never be portable.
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The Fast Interrupts WG agreed to define a distinction between low cost and high performance microcontrollers, because there may be a fork in the architecture due to different interrupt requirements.