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coastalwhite opened this issue Aug 6, 2023 · 3 comments
Open
2 of 11 tasks

Tracking Issue for RISC-V Ratified Extensions Intrinsics #114544

coastalwhite opened this issue Aug 6, 2023 · 3 comments
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A-floating-point Area: Floating point numbers and arithmetic A-SIMD Area: SIMD (Single Instruction Multiple Data) A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. C-tracking-issue Category: An issue tracking the progress of sth. like the implementation of an RFC O-riscv Target: RISC-V architecture T-libs-api Relevant to the library API team, which will review and decide on the PR/issue.

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@coastalwhite
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coastalwhite commented Aug 6, 2023 •
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This issue tracks the implementation of all the intrinsics linked to the Ratified RISC-V Extensions. The, not yet stable intrinsics are behind the riscv_ext_intrinsics nightly feature.

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Implementation History
@coastalwhite coastalwhite added C-tracking-issue Category: An issue tracking the progress of sth. like the implementation of an RFC T-libs-api Relevant to the library API team, which will review and decide on the PR/issue. labels Aug 6, 2023
coastalwhite added a commit to coastalwhite/rust that referenced this issue Aug 6, 2023
@coastalwhite
Add the riscv_ext_intrinsics feature for rust-lang#114544
e7f601d
This was referenced Aug 6, 2023
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@coastalwhite coastalwhite mentioned this issue Aug 16, 2023
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@coastalwhite
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Two additional points:

  1. Upcoming PRs should use the rustc_legacy_const_generics for immediate values instead.
  2. Prefer LLVM intrinsics to assembly. Intrinsics can be found here.

@coastalwhite
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Entropy Source of the Cryptographic Scalar Extension are not implemented in LLVM. Therefore, it should be implemented with inline assembly and is not part of the implemented intrinsics.

@coastalwhite
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Extensions such as Zfinx, Zdinx and Zhinx are all done by LLVM without intrinsics and therefore don't have to be done.

This was referenced Sep 30, 2023
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This was referenced Oct 26, 2023
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bors added a commit to rust-lang-ci/rust that referenced this issue Oct 30, 2023
@bors
Auto merge of rust-lang#116485 - coastalwhite:stabilize-riscv-target-…
91bbdd9 
…features, r=Amanieu

Stabilize Ratified RISC-V Target Features

Stabilization PR for the ratified RISC-V target features. This stabilizes some of the target features tracked by rust-lang#44839. This is also a part of rust-lang#114544 and eventually needed for the RISC-V part of rust-lang/rfcs#3268.

There is a similar PR for the the stdarch crate which can be found at rust-lang/stdarch#1476.

This was briefly discussed on Zulip
(https://rust-lang.zulipchat.com/#narrow/stream/250483-t-compiler.2Frisc-v/topic/Stabilization.20of.20RISC-V.20Target.20Features/near/394793704).

Specifically, this PR stabilizes the:
* Atomic Instructions (A) on v2.0
* Compressed Instructions (C) on v2.0
* ~Double-Precision Floating-Point (D) on v2.2~
* ~Embedded Base (E) (Given as `RV32E` / `RV64E`) on v2.0~
* ~Single-Precision Floating-Point (F) on v2.2~
* Integer Multiplication and Division (M) on v2.0
* ~Vector Operations (V) on v1.0~
* Bit Manipulations (B) on v1.0 listed as `zba`, `zbc`, `zbs`
* Scalar Cryptography (Zk) v1.0.1 listed as `zk`, `zkn`, `zknd`, `zkne`, `zknh`, `zkr`, `zks`, `zksed`, `zksh`, `zkt`, `zbkb`, `zbkc` `zkbx`
* ~Double-Precision Floating-Point in Integer Register (Zdinx) on v1.0~
* ~Half-Precision Floating-Point (Zfh) on v1.0~
* ~Minimal Half-Precision Floating-Point (Zfhmin) on v1.0~
* ~Single-Precision Floating-Point in Integer Register (Zfinx) on v1.0~
* ~Half-Precision Floating-Point in Integer Register (Zhinx) on v1.0~
* ~Minimal Half-Precision Floating-Point in Integer Register (Zhinxmin) on v1.0~

r? `@Amanieu`
endeneer added a commit to endeneer/hypocaust-2 that referenced this issue Nov 30, 2023
@endeneer
main: Enable riscv_ext_intrinsics feature
14db20e 
This commit is to solve the following build error:
```
error[E0658]: use of unstable library feature 'riscv_ext_intrinsics'
   --> src/guest/vmexit.rs:236:9
    |
236 |         core::arch::riscv64::hfence_gvma_all();
    |         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
    |
    = note: see issue #114544 <rust-lang/rust#114544> for more information
    = help: add `#![feature(riscv_ext_intrinsics)]` to the crate attributes to enable
```

Signed-off-by: Tan En De <[email protected]>
@zachs18 zachs18 mentioned this issue Feb 8, 2024
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@Amanieu Amanieu mentioned this issue Mar 10, 2024
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3 tasks
@workingjubilee workingjubilee added O-riscv Target: RISC-V architecture A-floating-point Area: Floating point numbers and arithmetic A-SIMD Area: SIMD (Single Instruction Multiple Data) A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. labels Nov 5, 2024
@workingjubilee workingjubilee mentioned this issue Nov 5, 2024
Open
This was referenced Mar 22, 2025
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Zalathar added a commit to Zalathar/rust that referenced this issue Apr 2, 2025
@Zalathar
Rollup merge of rust-lang#138823 - a4lg:riscv-feature-addition-base-i…
6aec7de 
…, r=Amanieu

rustc_target: RISC-V: add base `I`-related important extensions

Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria:

*   Formerly a part of the `I` extension and splitted thereafter (now ratified as `I` + `Zifencei` + `Zicsr` + `Zicntr` + `Zihpm`) or
*   Dicoverable from newer versions of the Linux kernel and implemented as a part of `std_detect`'s feature (`Zihintpause`) and
*   Available on LLVM 18.

This is based on [the latest ratified ISA Manuals (version 20240411)](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications).

LLVM Definitions:

*   [`Zifencei`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L133-L137)
*   [`Zicsr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L116-L120)
*   [`Zicntr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L122-L124)
*   [`Zihpm`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L153-L155)
*   [`Zihintpause`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L139-L144)

Additional (1):
One of those, `Zicsr`, is a dependency of many other ISA extensions and this commit adds correct dependencies to `Zicsr`.

Additional (2):
In RISC-V, `G` is an abbreviation of following extensions:
*   `I`
*   `M`
*   `A`
*   `F`
*   `D`
*   `Zicsr` (although implied by `F`)
*   `Zifencei`

and all RISC-V targets with the `G` abbreviation and targets for Android / VxWorks are updated accordingly.

Note:

Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC.  For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates `riscv32-wrs-vxworks` though).

--------

This is the version 4.
`Ztso` in the original proposal is removed on the PR version 2 due to the minimum LLVM version (non-experimental `Ztso` requires LLVM 19 while minimum LLVM version of Rust is 18). This is not back in PR version 3 and 4 after noticing adding `Ztso` is possible by checking host LLVM version because PR version 3 introduces compiler target changes (and adding more extensions would complicate the problems; sorry `Zihintpause`).

Version 4:
*   Fixed some commit messages,
*   Added Android / VxWorks targets to imply `G` and
*   Added an implication from `Zve32x` to `Zicsr` (which makes all vector extension subsets to imply `Zicsr`)
    since rust-lang#138742 is now merged.

Related:
*   rust-lang#44839
    (`riscv_target_feature`)
*   rust-lang#114544
    (This PR can be a prerequisite of resolving a part of that tracking issue)
*   rust-lang#138742
    (Touches the same place and vector extensions depend on `Zicsr`)

NOT Related but linked:
*   rust-lang#132618
    (This PR won't be blocked by this issue since none of those extensions do not change the ABI)

`@rustbot` r? `@Amanieu`
`@rustbot` label +T-compiler +O-riscv +A-target-feature
rust-timer added a commit to rust-lang-ci/rust that referenced this issue Apr 2, 2025
@rust-timer
Unrolled build for rust-lang#138823
18ce4f1 
Rollup merge of rust-lang#138823 - a4lg:riscv-feature-addition-base-i, r=Amanieu

rustc_target: RISC-V: add base `I`-related important extensions

Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria:

*   Formerly a part of the `I` extension and splitted thereafter (now ratified as `I` + `Zifencei` + `Zicsr` + `Zicntr` + `Zihpm`) or
*   Dicoverable from newer versions of the Linux kernel and implemented as a part of `std_detect`'s feature (`Zihintpause`) and
*   Available on LLVM 18.

This is based on [the latest ratified ISA Manuals (version 20240411)](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications).

LLVM Definitions:

*   [`Zifencei`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L133-L137)
*   [`Zicsr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L116-L120)
*   [`Zicntr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L122-L124)
*   [`Zihpm`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L153-L155)
*   [`Zihintpause`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L139-L144)

Additional (1):
One of those, `Zicsr`, is a dependency of many other ISA extensions and this commit adds correct dependencies to `Zicsr`.

Additional (2):
In RISC-V, `G` is an abbreviation of following extensions:
*   `I`
*   `M`
*   `A`
*   `F`
*   `D`
*   `Zicsr` (although implied by `F`)
*   `Zifencei`

and all RISC-V targets with the `G` abbreviation and targets for Android / VxWorks are updated accordingly.

Note:

Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC.  For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates `riscv32-wrs-vxworks` though).

--------

This is the version 4.
`Ztso` in the original proposal is removed on the PR version 2 due to the minimum LLVM version (non-experimental `Ztso` requires LLVM 19 while minimum LLVM version of Rust is 18). This is not back in PR version 3 and 4 after noticing adding `Ztso` is possible by checking host LLVM version because PR version 3 introduces compiler target changes (and adding more extensions would complicate the problems; sorry `Zihintpause`).

Version 4:
*   Fixed some commit messages,
*   Added Android / VxWorks targets to imply `G` and
*   Added an implication from `Zve32x` to `Zicsr` (which makes all vector extension subsets to imply `Zicsr`)
    since rust-lang#138742 is now merged.

Related:
*   rust-lang#44839
    (`riscv_target_feature`)
*   rust-lang#114544
    (This PR can be a prerequisite of resolving a part of that tracking issue)
*   rust-lang#138742
    (Touches the same place and vector extensions depend on `Zicsr`)

NOT Related but linked:
*   rust-lang#132618
    (This PR won't be blocked by this issue since none of those extensions do not change the ABI)

`@rustbot` r? `@Amanieu`
`@rustbot` label +T-compiler +O-riscv +A-target-feature
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A-floating-point Area: Floating point numbers and arithmetic A-SIMD Area: SIMD (Single Instruction Multiple Data) A-target-feature Area: Enabling/disabling target features like AVX, Neon, etc. C-tracking-issue Category: An issue tracking the progress of sth. like the implementation of an RFC O-riscv Target: RISC-V architecture T-libs-api Relevant to the library API team, which will review and decide on the PR/issue.
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