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Merged
merged 8 commits into from
Jul 29, 2017
Merged

More Altivec Intrinsics #43492

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ccdfd7f
Add mradds to the powerpc intrinsics
lu-zero Jul 24, 2017
4f6c03e
Add Vector Compare Bounds Floating-Point
lu-zero Jul 26, 2017
e2b5a6b
Add Vector Compare Equal
lu-zero Jul 26, 2017
a1995d3
Add Vector Compare Greater-Than
lu-zero Jul 26, 2017
ade5ead
Add support for the Power8 and Power9 features on PowerPC
lu-zero Jul 27, 2017
a718c81
Add support for Vector Maximum on PowerPC
lu-zero Jul 27, 2017
cbce0aa
Add support for Vector Minimum on PowerPC
lu-zero Jul 27, 2017
c471020
Make LLVMRustHasFeature more robust
lu-zero Jul 28, 2017
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60 changes: 58 additions & 2 deletions src/etc/platform-intrinsics/powerpc.json
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Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,15 @@
"intrinsic_prefix": "_vec_",
"llvm_prefix": "llvm.ppc.altivec.",
"number_info": {
"unsigned": {},
"signed": {}
"unsigned": {
"kind" : "u",
"data_type_short": { "8": "b", "16": "h", "32": "w", "64": "d" }
},
"signed": {
"kind" : "s",
"data_type_short": { "8": "b", "16": "h", "32": "w", "64": "d" }
},
"float": {}
},
"width_info": {
"128": { "width": "" }
Expand All @@ -16,6 +23,55 @@
"llvm": "vperm",
"ret": "s32",
"args": ["0", "0", "s8"]
},
{
"intrinsic": "mradds",
"width": [128],
"llvm": "vmhraddshs",
"ret": "s16",
"args": ["0", "0", "0"]
},
{
"intrinsic": "cmpb",
"width": [128],
"llvm": "vcmpbfp",
"ret": "s32",
"args": ["f32", "f32"]
},
{
"intrinsic": "cmpeq{0.data_type_short}",
"width": [128],
"llvm": "vcmpequ{0.data_type_short}",
"ret": "s(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "cmpgt{1.kind}{1.data_type_short}",
"width": [128],
"llvm": "vcmpgt{1.kind}{1.data_type_short}",
"ret": "s(8-32)",
"args": ["0u", "1"]
},
{
"intrinsic": "cmpgt{1.kind}{1.data_type_short}",
"width": [128],
"llvm": "vcmpgt{1.kind}{1.data_type_short}",
"ret": "s(8-32)",
"args": ["0", "1"]
},
{
"intrinsic": "max{0.kind}{0.data_type_short}",
"width": [128],
"llvm": "vmax{0.kind}{0.data_type_short}",
"ret": "i(8-32)",
"args": ["0", "0"]
},
{
"intrinsic": "min{0.kind}{0.data_type_short}",
"width": [128],
"llvm": "vmin{0.kind}{0.data_type_short}",
"ret": "i(8-32)",
"args": ["0", "0"]
}
]
}
115 changes: 115 additions & 0 deletions src/librustc_platform_intrinsics/powerpc.rs
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Expand Up @@ -27,6 +27,121 @@ pub fn find(name: &str) -> Option<Intrinsic> {
output: &::I32x4,
definition: Named("llvm.ppc.altivec.vperm")
},
"_vec_mradds" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &INPUTS },
output: &::I16x8,
definition: Named("llvm.ppc.altivec.vmhraddshs")
},
"_vec_cmpb" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS },
output: &::I32x4,
definition: Named("llvm.ppc.altivec.vcmpbfp")
},
"_vec_cmpeqb" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
output: &::I8x16,
definition: Named("llvm.ppc.altivec.vcmpequb")
},
"_vec_cmpeqh" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
output: &::I16x8,
definition: Named("llvm.ppc.altivec.vcmpequh")
},
"_vec_cmpeqw" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
output: &::I32x4,
definition: Named("llvm.ppc.altivec.vcmpequw")
},
"_vec_cmpgtub" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
output: &::I8x16,
definition: Named("llvm.ppc.altivec.vcmpgtub")
},
"_vec_cmpgtuh" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
output: &::I16x8,
definition: Named("llvm.ppc.altivec.vcmpgtuh")
},
"_vec_cmpgtuw" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
output: &::I32x4,
definition: Named("llvm.ppc.altivec.vcmpgtuw")
},
"_vec_cmpgtsb" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
output: &::I8x16,
definition: Named("llvm.ppc.altivec.vcmpgtsb")
},
"_vec_cmpgtsh" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
output: &::I16x8,
definition: Named("llvm.ppc.altivec.vcmpgtsh")
},
"_vec_cmpgtsw" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
output: &::I32x4,
definition: Named("llvm.ppc.altivec.vcmpgtsw")
},
"_vec_maxsb" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
output: &::I8x16,
definition: Named("llvm.ppc.altivec.vmaxsb")
},
"_vec_maxub" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
output: &::U8x16,
definition: Named("llvm.ppc.altivec.vmaxub")
},
"_vec_maxsh" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
output: &::I16x8,
definition: Named("llvm.ppc.altivec.vmaxsh")
},
"_vec_maxuh" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
output: &::U16x8,
definition: Named("llvm.ppc.altivec.vmaxuh")
},
"_vec_maxsw" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
output: &::I32x4,
definition: Named("llvm.ppc.altivec.vmaxsw")
},
"_vec_maxuw" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
output: &::U32x4,
definition: Named("llvm.ppc.altivec.vmaxuw")
},
"_vec_minsb" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS },
output: &::I8x16,
definition: Named("llvm.ppc.altivec.vminsb")
},
"_vec_minub" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS },
output: &::U8x16,
definition: Named("llvm.ppc.altivec.vminub")
},
"_vec_minsh" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS },
output: &::I16x8,
definition: Named("llvm.ppc.altivec.vminsh")
},
"_vec_minuh" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS },
output: &::U16x8,
definition: Named("llvm.ppc.altivec.vminuh")
},
"_vec_minsw" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS },
output: &::I32x4,
definition: Named("llvm.ppc.altivec.vminsw")
},
"_vec_minuw" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS },
output: &::U32x4,
definition: Named("llvm.ppc.altivec.vminuw")
},
_ => return None,
})
}
5 changes: 4 additions & 1 deletion src/librustc_trans/llvm_util.rs
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Expand Up @@ -80,7 +80,10 @@ const X86_WHITELIST: &'static [&'static str] = &["avx\0", "avx2\0", "bmi\0", "bm

const HEXAGON_WHITELIST: &'static [&'static str] = &["hvx\0", "hvx-double\0"];

const POWERPC_WHITELIST: &'static [&'static str] = &["altivec\0", "vsx\0"];
const POWERPC_WHITELIST: &'static [&'static str] = &["altivec\0",
"power8-altivec\0", "power9-altivec\0",
"power8-vector\0", "power9-vector\0",
"vsx\0"];

pub fn target_features(sess: &Session) -> Vec<Symbol> {
let target_machine = create_target_machine(sess);
Expand Down
20 changes: 7 additions & 13 deletions src/rustllvm/PassWrapper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -181,20 +181,14 @@ extern "C" bool LLVMRustHasFeature(LLVMTargetMachineRef TM,
TargetMachine *Target = unwrap(TM);
const MCSubtargetInfo *MCInfo = Target->getMCSubtargetInfo();
const FeatureBitset &Bits = MCInfo->getFeatureBits();
const llvm::SubtargetFeatureKV *FeatureEntry;

#define SUBTARGET(x) \
if (MCInfo->isCPUStringValid(x##SubTypeKV[0].Key)) { \
FeatureEntry = x##FeatureKV; \
} else

GEN_SUBTARGETS { return false; }
#undef SUBTARGET

while (strcmp(Feature, FeatureEntry->Key) != 0)
FeatureEntry++;
#if LLVM_VERSION_GE(4, 0)
const ArrayRef<SubtargetFeatureKV> FeatTable = MCInfo->getFeatureTable();

return (Bits & FeatureEntry->Value) == FeatureEntry->Value;
for (auto &FeatureEntry : FeatTable)
if (!strcmp(FeatureEntry.Key, Feature))
return (Bits & FeatureEntry.Value) == FeatureEntry.Value;
#endif
return false;
}

enum class LLVMRustCodeModel {
Expand Down
2 changes: 1 addition & 1 deletion src/test/run-make/print-cfg/Makefile
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Expand Up @@ -5,7 +5,7 @@ all: default
$(RUSTC) --target x86_64-pc-windows-gnu --print cfg | grep x86_64
$(RUSTC) --target i686-pc-windows-msvc --print cfg | grep msvc
$(RUSTC) --target i686-apple-darwin --print cfg | grep macos
$(RUSTC) --target i686-unknown-linux-gnu --print cfg | grep sse2
$(RUSTC) --target i686-unknown-linux-gnu --print cfg | grep gnu

ifdef IS_WINDOWS
default:
Expand Down
1 change: 1 addition & 0 deletions src/test/run-pass/sse2.rs
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Expand Up @@ -7,6 +7,7 @@
// <LICENSE-MIT or http://opensource.org/licenses/MIT>, at your
// option. This file may not be copied, modified, or distributed
// except according to those terms.
// min-llvm-version 4.0

#![feature(cfg_target_feature)]

Expand Down