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‎doc/TODO.md‎

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# TODO
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* why does // val pcReg = RegInit(-4.S(32.W).asUInt) result in failing tests?q
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- do not execute first instruction from on-chip memory
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- but start with -4
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- also remove init address register from instruction ROM
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* UART
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* Check if gcc can do RV32E
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* Get the C code compilation better integrated (with a reasonable linker.ld)
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* Get C compiled apps running (more than hello)
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* Update simulation (and C/asm code) for new address mapping and checking for ready
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* Why do I have read and write addresses in the data memory, when only one will happen at a time?
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- Check others
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* Something is fishy with testing, as SingleCycle works (even without branch)
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* Two tests fail with co-simulation when adding stall to fetch (the toggle)
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* width.s should not fail in the ISA simulator
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- string should work as well, do we need a linker script?
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- Work on failing simple tests (Simulator and Wildcat)
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* Memory range checks
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* Aim to have same interface for pipeline and single cycle
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- reuse tests
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* Forwarding from ALU/memory to address computation is missing.
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* 4/5 stages stall on load use hazard is missing (not covered by the tests)
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* Single cycle is not finished - tests are failing, disabled
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* 3/4/5 load and use as address is wrong (need a forward to the adder)
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- test missing
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* ecall, ebreak
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* csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
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* At some point try to run the "real" RISC-V tests (need quite some infra)
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* Traps on not implemented instructions and unaligned access
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* Better names for signals (e.g., for those with a feedback, e.g., RF write)
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* Maybe commit the .elf files for faster tests
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* Maybe add some tracing facility
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* compare code can be optimized (see Tommy's code, or JOP code)
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* Get Rust bare metal running
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* Move selection between register and imm back into decode
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- maybe more of the muxing could be done there
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- probably branch target computation
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- or the whole branching itself
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* ecall
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* Maybe check the .elf files in for faster tests
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* What are the types of immediate values? mostly signed or mostly unsigned?
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* And much more not listed here, e.g. caches, interconnect, newlib, ...
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* Write documentation
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* [ ] Sort the TODO list
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* [ ] Change memory interface to `PipeCon`
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* [ ] Have a better drawing of `PipeCon` (in soc-comm)
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* [ ] Start collecting information on other core interfaces (in my paper)
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# Unsorted TODOs
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* [ ] why does // val pcReg = RegInit(-4.S(32.W).asUInt) result in failing tests?
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- [ ] Do not execute the first instruction from on-chip memory
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- [ ] but start PC with -4
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- [ ] remove initialization of the address register from the instruction ROM
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* [ ] UART
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* [ ] Check if gcc can do RV32E
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* [ ] Get the C code compilation better integrated (with a reasonable linker.ld)
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* [ ] Get C compiled apps running (more than hello)
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* [ ] Update simulation (and C/asm code) for new address mapping and checking for ready
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* [ ] Why do I have read and write addresses in the data memory, when only one will happen at a time?
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- [ ] Check others
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* [ ] Something is fishy with testing, as SingleCycle works (even without branch)
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* [ ] Two tests fail with co-simulation when adding stall to fetch (the toggle)
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* [ ] width.s should not fail in the ISA simulator
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- [ ] string should work as well, do we need a linker script?
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- [ ] Work on failing simple tests (Simulator and Wildcat)
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* [ ] Memory range checks
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* [ ] Aim to have the same interface for pipeline and single cycle
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- [ ] reuse tests
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* [ ] Forwarding from ALU/memory to address computation is missing.
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* [ ] 4/5 stages stall on load use hazard is missing (not covered by the tests)
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* [ ] Single cycle is not finished - tests are failing, disabled
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* [ ] 3/4/5 load and use as address is wrong (need a forward to the adder)
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- [ ] test missing
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* [ ] ecall, ebreak
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* [ ] csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
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* [ ] At some point try to run the "real" RISC-V tests (need quite some infra)
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* [ ] Traps on not implemented instructions and unaligned access
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* [ ] Better names for signals (e.g., for those with a feedback, e.g., RF write)
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* [ ] Maybe commit the .elf files for faster tests
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* [ ] Maybe add some tracing facility
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* [ ] compare code can be optimized (see Tommy's code, or JOP code)
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* [ ] Get Rust bare metal running
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* [ ] Move selection between register and imm back into decode
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- [ ] maybe more of the muxing could be done there
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- [ ] probably branch target computation
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- [ ] or the whole branching itself
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* [ ] ecall
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* [ ] Maybe check the .elf files in for faster tests
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* [ ] What are the types of immediate values? mostly signed or mostly unsigned?
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* [ ] And much more not listed here, e.g. caches, interconnect, newlib, ...
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* [ ] Write documentation
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## Better Naming
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* wrEna is later called valid
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* [ ] wrEna is later called valid
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# Docu Start
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JALR uses the ALU with the immediate similar to ADDI.
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# Further Reading
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* A nice single cycle implementation: /Users/martin/data/dtu/teaching/cae/exam2022/Final Assignment ...
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* Checkout: https://github.com/SpinalHDL/VexRiscv (has a lot of info)
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* unaligned access is not too hard with byte-wise access
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* or trap on unaligned access
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* Explore compiler options
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* Explore https://inst.eecs.berkeley.edu/~cs250/fa10/ (for chip design course)
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* https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/tut3-riscv.pdf
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* Checkout https://github.com/ucb-bar/riscv-mini
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* Checkout https://github.com/bobbl/rudolv (Joerg Mische), might be close to Wildcat plan
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* List of RV cores with IDs: https://github.com/riscv/riscv-isa-manual/blob/latex/marchid.md
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* Ibex is 2 stages: https://ibex-core.readthedocs.io/en/latest/03_reference/pipeline_details.html
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* Checkout random instruction generator: https://ibex-core.readthedocs.io/en/latest/03_reference/pipeline_details.html
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* Checkout https://github.com/SpinalHDL/VexiiRiscv
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* Interesting core: https://github.com/darklife/darkriscv
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To be included in my paper.
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* [ ] A nice single cycle implementation: /Users/martin/data/dtu/teaching/cae/exam2022/Final Assignment ...
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* [ ] Checkout: https://github.com/SpinalHDL/VexRiscv (has a lot of info)
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* [ ] unaligned access is not too hard with byte-wise access
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* [ ] or trap on unaligned access
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* [ ] Explore compiler options
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* [ ] Explore https://inst.eecs.berkeley.edu/~cs250/fa10/ (for chip design course)
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* [ ] https://inst.eecs.berkeley.edu/~cs250/fa10/handouts/tut3-riscv.pdf
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* [ ] Checkout https://github.com/ucb-bar/riscv-mini
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* [ ] Checkout https://github.com/bobbl/rudolv (Joerg Mische), might be close to Wildcat plan
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* [ ] List of RV cores with IDs: https://github.com/riscv/riscv-isa-manual/blob/latex/marchid.md
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* [ ] Ibex is 2 stages: https://ibex-core.readthedocs.io/en/latest/03_reference/pipeline_details.html
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* [ ] Checkout random instruction generator: https://ibex-core.readthedocs.io/en/latest/03_reference/pipeline_details.html
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* [ ] Checkout https://github.com/SpinalHDL/VexiiRiscv
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* [ ] Interesting core: https://github.com/darklife/darkriscv

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