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[Perf] [AMD] dsv4: FP4 indexer on aiter's row-group kernel for decode and target-verify (5/8) - #44006

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HaiShaw merged 10 commits into
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HaiShaw:amd/dsv4-fp4-indexer-rowgroup
Oct 16, 2026
Merged

HaiShaw merged 10 commits into
sgl-project:mainfrom
HaiShaw:amd/dsv4-fp4-indexer-rowgroup

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@kkHuang-amd

@kkHuang-amd kkHuang-amd commented Oct 13, 2026 •

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Motivation

The FP4 indexer re-reads each key per query row. aiter's row-group FP4 MQA logits kernel (ROCm/aiter#6145) shares key loads across a request's rows. This uses it for V4.1 low-ratio layers and, opt-in, for the DeepSeek-V4 C4 indexer. Includes #43073 (not merged yet).

Depends on: #43073 (open, included here); ROCm/aiter#6145 (in aiter main, needs the aiter pin bump in #44035).

Modifications

  • V4.1 low-ratio indexer on the row-group kernel with candidate-only scoring ([AMD][V4.1] Optimize FP4 indexer with shared K loads and candidate-only scoring #43073; SGLANG_HIP_FP4_INDEXER_ROWGROUP, default on for HIP; page-8 index-K pool SGLANG_HIP_DSV41_INDEX_K_PAGE8, default off).
  • DeepSeek-V4 C4 indexer decode and target-verify (>= 64 rows) on the row-group kernel, workspace built inside the graph (SGLANG_HIP_DSV4_C4_INDEXER_ROWGROUP, default off).
  • All three paths fall back to the schedule kernels / page-64 pool with a warning when the installed aiter has no row-group kernel; tests skip there.

Accuracy Tests

GSM8K: main 0.953 -> 0.948 (default), 0.946-0.954 with SGLANG_HIP_DSV4_C4_INDEXER_ROWGROUP=1 (aiter 02575f1c3a).

Speed Tests and Profiling

From #43073, DeepSeek-V4.1-Flash TP2, 68000 in / 200 out, total throughput: c1 +0.7%, c4 +1.2%, c16 +2.4%.
C4 rowgroup, bench_dsv4_c4_indexer_rowgroup_hip.py, indexer time per step over 30 C4 layers incl. workspace, max context 65536: decode bs16 ctx 8K 197 -> 117 us (1.68x), bs64 ctx 64K 621 -> 525 us (1.18x); 4-row verify bs64 ctx 64K 1262 -> 1076 us (1.17x), bs16-32 ctx 8K about 5% slower.

Co-authored-by: AMD-yanfeiwang 256076023+AMD-yanfeiwang@users.noreply.github.com

Checklist

Review and Merge Process

  1. Ping Merge Oncalls to start the process. See the PR Merge Process.
  2. Get approvals from CODEOWNERS and other reviewers.
  3. Trigger CI tests with comments or contact authorized users to do so.
    • Common commands include /tag-and-rerun-ci, /tag-run-ci-label, /rerun-failed-ci
  4. After green CI and required approvals, ask Merge Oncalls or people with Write permission to merge the PR.

CI States

Latest PR Test (Base): ❌ Run #38719474783
Latest PR Test (Extra): ❌ Run #38719474489
Latest PR Test (AMD ROCm 10): ❌ Run #38719474736

Duyi-Wang and others added 4 commits October 13, 2026 05:31
…ly scoring (sgl-project#43073)

Squashed from sgl-project#43073 (head 60abf99).

Conflict resolved against main 8afe107: deepseek_v4_backend_hip_radix.py import list keeps both _prefill_graph_max_seq_len (main sgl-project#42570) and _as_int_list (this PR).
…up kernel

SGLANG_HIP_DSV4_C4_INDEXER_ROWGROUP=1 (default off) moves the DeepSeek-V4 C4
indexer's DECODE and DSpark TARGET_VERIFY scoring onto aiter's row-group FP4 MQA
logits kernel (sgl-project#6145), through the sgl-project#43073 wrapper (rowgroup_paged_mqa_logits):

* the backend builds the row-group decode workspace in the graph for decode
  (one row a request) and for a target-verify of >= C4_ROWGROUP_MIN_VERIFY_ROWS
  (64) rows (a request's draft rows one sequence, sharing each key load); such
  a verify skips the prefill schedule refresh. Smaller verifies, and verifies
  whose logits outgrow the prefill budget, keep the prefill kernel.
* the block table is padded to one width for the server's life
  (rowgroup_table_columns over max(context_len, req_to_token width)), so the
  kernel compiles one variant per row grouping.
* the indexer scores such a verify step like decode: one launch, unchunked.
* a row-group workspace left stale by DP padding is rebuilt per row on the same
  table width instead of falling back to the schedule kernels.
* off when the installed aiter has no row-group kernel (warning).

The C4 index-K pool is unchanged: (pages, 1, 4, 64, 16) payload + (pages, 1, 4,
64) scale is aiter's page-64 row-group layout byte for byte.

Tests: test_fp4_indexer_hip.py gains DSv4 decode / verify shapes (4 and 7 rows,
ragged contexts, poisoned logits tail) against the schedule kernels, the FP4
reference and the top-k v2 (1024) selection, plus stale-workspace and in-graph
replay cases. bench_dsv4_c4_indexer_rowgroup_hip.py measures the kernels and
the per-step totals.


The row-group FP4 MQA logits kernel needs aiter >= ROCm/aiter#6145.
- SGLANG_HIP_DSV41_INDEX_K_PAGE8 now falls back to the page-64 index-K pool
  with a warning when the installed aiter lacks it (it raised ImportError
  mid-serving before); the C4 decode/verify switch already checked.
- test_fp4_indexer_hip.py: the row-group / page8 tests skip on such aiter.
…project#6145

SGLANG_HIP_FP4_INDEXER_ROWGROUP defaults on for HIP, so V4.1 low-ratio
decode built row-group workspaces and raised ImportError on an aiter without
the row-group kernel (e.g. the current e7d2453f pin). It now falls back to the
schedule kernels with a warning there.
…stub backend

test_dsv4_hip_bcg_metadata.py builds DeepseekV4HipRadixBackend with
object.__new__ and sets the attributes init_forward_metadata_in_graph reads;
it now also sets _fp4_c4_rowgroup_columns (None: row-group C4 indexer off).
@Duyi-Wang Duyi-Wang removed the run-ci-extra CI: also run the extra suite (requires run-ci) label Oct 15, 2026
@kkHuang-amd kkHuang-amd added the run-ci-extra CI: also run the extra suite (requires run-ci) label Oct 15, 2026
@kkHuang-amd kkHuang-amd changed the title [AMD][DSV4][5/8] FP4 indexer on aiter's row-group kernel for decode and target-verify [Perf] [AMD] dsv4: FP4 indexer on aiter's row-group kernel for decode and target-verify (5/8) Oct 16, 2026

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HIP specific

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amd deepseek jit-kernel memory-pool run-ci CI: run the baseline test suite on this PR run-ci-extra CI: also run the extra suite (requires run-ci)

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