Padring generator upgrade

lambdalib/iolib/README.md

@@ -0,0 +1,80 @@
+# IOLIB
+
+## Cell Listing
+
+| Cell                             | Type    | Description                 |
+| ---------------------------------|---------|-----------------------------|
+[[la_iobidir](./rtl/la_iobidir.v)  | Digital | Bidirectional
+[la_ioinput](./rtl/la_ioinput.v)   | Digital | Input
+[la_ioxtal](./rtl/la_ioxtal.v)     | Digital | Xtal tranceiver
+[la_iorxdiff](./rtl/la_iorxdiff.v) | Digital | Differential input
+[la_iotxdiff](./rtl/la_iotxdiff.v) | Digital | Differential output
+[la_ioanalog](./rtl/la_ioanalog.v) | Analog  | Pass through ESD protection
+[la_iovdd](./rtl/la_iovdd.v)       | Supply  | Core power
+[la_iovss](./rtl/la_iovss.v)       | Supply  | Core ground
+[la_iovddio](./rtl/la_iovddio.v)   | Supply  | IO  power
+[la_iovssio](./rtl/la_iovssio.v)   | Supply  | IO ground
+[la_iovdda](./rtl/la_iovdda.v)     | Supply  | Analog power
+[la_iovssa](./rtl/la_iovssa.v)     | Supply  | Analog ground
+[la_iopoc](./rtl/la_iopoc.v)       | Supply  | Power on control
+[la_iocorner](./rtl/la_iocorner.v) | Supply  | Corner connector
+[la_ioclamp](./rtl/la_ioclamp.v)   | Supply  | ESD clamp
+[la_iocut](./rtl/la_iocut.v)       | Supply  | Power ring cutter
+
+## PARAMETERS
+
+### CFGW
+The `CFGW` parameter defines the width of the configuration bus of the io cell. IO cells generally include a set of configuration inputs for things like drive strength and operating modes. Setting `CFGW` to a large value (eg. 16/32) should have zero impact on the design as the extra bus bits get optimized away during implementation. The connection between the generic `CFG` bus and the technology specific IO cell is done within the techology specific cell wrapper library.
+
+For la_bidir, the first 8 bits of the configuration bus are reserved for the functionality shown in the table below.
+
+| Bit       | Description                                     |
+|-----------|-------------------------------------------------|
+ CFG[0]     | slew rate control (0=fast, 1 =slow)             |
+ CFG[1]     | schmitt trigger select (0=CMOS, 1=schmitt)      |
+ CFG[2]     | pull enable (0=no pull, 1=enables weak pull)    |
+ CFG[3]     | pull select (1=pull up, 0=pull down)            |
+ CFG[7:4]   | drive strength                                  |
+
+#### RINGW
+The `RINGW` parameter specifies the number of signals within the power bus that connects all of the io cells together within the padring.
+
+### SIDE
+The `SIDE` parameter indicates the placement of a cell instances within a padring.Legal values for `SIDE` are: "NO" (north/top), "EA" (east/right), "WE" (west/left), "SO" (south/bottom). The parameter can be used by the technology specific implementation of `iolib` to selec the native orientation of the cell. Modern process nodes place restrictions on the orientation of transistors and include vertical and horizontal version of all active io cells.
+
+### PROP
+The `PROP` parameter can be used by the technology specific `iolib` implementation to select between different variants of the `iolib` cell type. The `PROP` parameter is library specific and should only be used when absolutely necessary. Using this parameter means technology/ip information permeates up through the design (nullifying the benefits of lambdalib).
+
+## Cell Description
+
+## la_iobidir
+
+## la_ioinput
+
+## la_ioxtal
+
+## la_iorxdif
+
+## la_iotxdiff
+
+## la_ioanalog
+
+## la_iovdd
+
+## la_iovss
+
+## la_iovddio
+
+## la_iovssio
+
+## la_iovdda
+
+## la_iovssa
+
+## la_iopoc
+
+## la_iocorner
+
+## la_ioclamp
+
+## la_iocut

lambdalib/iolib/rtl/la_ioanalog.v

@@ -1,33 +1,36 @@
 /*****************************************************************************
- * Function: IO analog pass-through cell
+ * Function: Analog Passthrough IO cell
  * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
+ * ../README.md
+ *
  * aio[0] = pass through from pad (with esd clamp)
  * aio[1] = small series resistance
  * aio[2] = big series resistance
  *
  ****************************************************************************/
-module la_ioanalog #(
-    parameter TYPE  = "DEFAULT",  // cell type
-    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
-    parameter RINGW = 8           // width of io ring
-) (  // io pad signals
-    inout             pad,     // bidirectional pad signal
-    inout             vdd,     // core supply
-    inout             vss,     // core ground
-    inout             vddio,   // io supply
-    inout             vssio,   // io ground
-    inout [RINGW-1:0] ioring,  // generic io-ring interface
+module la_ioanalog
+  #(
+    parameter PROP = "DEFAULT", // cell property
+    parameter SIDE = "NO",      // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8         // width of io ring
+    )
+   (// io pad signals
+    inout             pad,    // bidirectional pad signal
+    inout             vdd,    // core supply
+    inout             vss,    // core ground
+    inout             vddio,  // io supply
+    inout             vssio,  // io ground
+    inout [RINGW-1:0] ioring, // generic ioring
     // core interface
-    inout [      2:0] aio      // analog core signal
-);
-
+    inout [2:0]       aio     // analog core signals
+    );
 
 `ifdef VERILATOR
-    // TODO!: input only for verilator bases simulation
+    // TODO!: input only for verilator based simulation
     assign aio[0] = pad;
     assign aio[1] = pad;
     assign aio[2] = pad;

lambdalib/iolib/rtl/la_iobidir.v

@@ -1,40 +1,36 @@
-/*****************************************************************************
- * Function: IO bi-directional buffer
+/**************************************************************************
+ * Function: Digital Bidirectional IO Buffer
  * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
- * This is a generic cell that defines the standard interface of the lambda
- * bidrectional buffer cell. It is only suitable for FPGA synthesis.
+ * ../README.md
  *
- * ASIC specific libraries will need to use the TYPE field to select an
- * appropriate hardcoded physical cell based on the the process constraints
- * and library composition. For example, modern nodes will usually have
- * different IP cells for the placing cells vvertically or horizontally.
- *
- ****************************************************************************/
-module la_iobidir #(
-    parameter TYPE  = "DEFAULT",  // cell type
-    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
-    parameter CFGW  = 16,         // width of core config bus
-    parameter RINGW = 8           // width of io ring
-) (  // io pad signals
-    inout              pad,     // bidirectional pad signal
-    inout              vdd,     // core supply
-    inout              vss,     // core ground
-    inout              vddio,   // io supply
-    inout              vssio,   // io ground
+ *************************************************************************/
+module la_iobidir
+  #(
+    parameter PROP = "DEFAULT", // cell property
+    parameter SIDE = "NO",      // "NO", "SO", "EA", "WE"
+    parameter CFGW = 16,        // width of core config bus
+    parameter RINGW = 8         // width of io ring
+    )
+   (// io pad signals
+    inout             pad,    // bidirectional pad signal
+    inout             vdd,    // core supply
+    inout             vss,    // core ground
+    inout             vddio,  // io supply
+    inout             vssio,  // io ground
     // core facing signals
-    input              a,       // input from core
-    output             z,       // output to core
-    input              ie,      // input enable, 1 = active
-    input              oe,      // output enable, 1 = active
-    inout  [RINGW-1:0] ioring,  // generic io-ring interface
-    input  [ CFGW-1:0] cfg      // generic config interface
-);
+    input             a,      // input from core
+    output            z,      // output to core
+    input             ie,     // input enable, 1 = active
+    input             oe,     // output enable, 1 = active
+    inout [RINGW-1:0] ioring, // generic io ring
+    input [CFGW-1:0]  cfg     // generic config interface
+    );
 
-    // to core
+   // to core
     assign z   = ie ? pad : 1'b0;
 
     // to pad

lambdalib/iolib/rtl/la_ioclamp.v

@@ -1,21 +1,25 @@
 /*****************************************************************************
- * Function: IO ESD clamp cell
+ * Function: ESD Clamp IO cell
  * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
+ * ../README.md
+ *
  ****************************************************************************/
-module la_ioclamp #(
-    parameter TYPE  = "DEFAULT",  // cell type
-    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
-    parameter RINGW = 8           // width of io ring
-) (  // io pad signals
-    inout             vdd,    // core supply
-    inout             vss,    // core ground
-    inout             vddio,  // io supply
-    inout             vssio,  // io ground
-    inout [RINGW-1:0] ioring  // generic io-ring interface
-);
+module la_ioclamp
+  #(
+    parameter PROP = "DEFAULT", // cell property
+    parameter SIDE = "NO",      // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8         // width of io ring
+    )
+   (// io pad signals
+    inout             vdd,   // core supply
+    inout             vss,   // core ground
+    inout             vddio, // io supply
+    inout             vssio, // io ground
+    inout [RINGW-1:0] ioring // generic io ring interface
+    );
 
 endmodule

lambdalib/iolib/rtl/la_iocorner.v

@@ -1,22 +1,25 @@
 /*****************************************************************************
- * Function: IO corner cell
+ * Function: Corner IO Cell
  * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
+ * ../README.md
  *
  ****************************************************************************/
-module la_iocorner #(
-    parameter TYPE  = "DEFAULT",  // cell type
-    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
-    parameter RINGW = 8           // width of io ring
-) (
-    inout             vdd,    // core supply
-    inout             vss,    // core ground
-    inout             vddio,  // io supply
-    inout             vssio,  // io ground
-    inout [RINGW-1:0] ioring  // generic io-ring interface
-);
+module la_iocorner
+  #(
+    parameter PROP = "DEFAULT", // cell property
+    parameter SIDE = "NO",      // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8         // width of io ring
+    )
+   (
+    inout             vdd,   // core supply
+    inout             vss,   // core ground
+    inout             vddio, // io supply
+    inout             vssio, // io ground
+    inout [RINGW-1:0] ioring // generic ioring interface
+    );
 
 endmodule

lambdalib/iolib/rtl/la_iocut.v

@@ -1,19 +1,24 @@
 /*****************************************************************************
- * Function: IO cut cell
+ * Function: Supply Ring Cut IO Cell
  * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
+ * ../README.md
  *
  ****************************************************************************/
-module la_iocut #(
-    parameter TYPE  = "DEFAULT",  // cell type
-    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
-    parameter RINGW = 8           // width of io ring
-) (
+module la_iocut
+  #(
+    parameter PROP = "DEFAULT", // cell property
+    parameter SIDE = "NO",      // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8         // width of io ring
+    )
+   (
     // ground never cut
     inout vss
-);
+    );
+
+   // TODO: interface?
 
 endmodule

lambdalib/iolib/rtl/la_ioinput.v

@@ -1,38 +1,34 @@
-/*****************************************************************************
- * Function: IO bi-directional buffer
+/**************************************************************************
+ * Function: Digital Input IO Cell
  * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
- * This is a generic cell that defines the standard interface of the lambda
- * bidrectional buffer cell. It is only suitable for FPGA synthesis.
+ * ../README.md
  *
- * ASIC specific libraries will need to use the TYPE field to select an
- * appropriate hardcoded physical cell based on the the process constraints
- * and library composition. For example, modern nodes will usually have
- * different IP cells for the placing cells vvertically or horizontally.
- *
- ****************************************************************************/
-module la_ioinput #(
-    parameter TYPE  = "DEFAULT",  // cell type
-    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
-    parameter CFGW  = 16,         // width of core config bus
-    parameter RINGW = 8           // width of io ring
-) (  // io pad signals
-    inout              pad,     // bidirectional pad signal
-    inout              vdd,     // core supply
-    inout              vss,     // core ground
-    inout              vddio,   // io supply
-    inout              vssio,   // io ground
+ *************************************************************************/
+module la_ioinput
+  #(
+    parameter PROP = "DEFAULT", // cell property
+    parameter SIDE = "NO",      // "NO", "SO", "EA", "WE"
+    parameter CFGW = 16,        // width of core config bus
+    parameter RINGW = 8         // width of io ring
+    )
+   (// io pad signals
+    inout             pad,    // input pad
+    inout             vdd,    // core supply
+    inout             vss,    // core ground
+    inout             vddio,  // io supply
+    inout             vssio,  // io ground
     // core facing signals
-    output             z,       // output to core
-    input              ie,      // input enable, 1 = active
-    inout  [RINGW-1:0] ioring,  // generic io-ring interface
-    input  [ CFGW-1:0] cfg      // generic config interface
-);
+    output            z,      // output to core
+    input             ie,     // input enable, 1 = active
+    inout [RINGW-1:0] ioring, // generic ioring interface
+    input [CFGW-1:0]  cfg     // generic config interface
+    );
 
-    // to core
-    assign z = ie ? pad : 1'b0;
+   // to core
+   assign z = ie ? pad : 1'b0;
 
 endmodule