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add clamp and add additional helper signals to poc #70

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Merged
merged 4 commits into from
Aug 16, 2024
Merged

add clamp and add additional helper signals to poc #70

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b720ea2
add clamp to ioside.v and provide pad input to clamp cell
gadfort Aug 15, 2024
41d8cc7
add cfg to la_iopoc
gadfort Aug 15, 2024
9ffd6cd
add missing comment for VDDIO
gadfort Aug 15, 2024
995d7ef
fix verilog lint
gadfort Aug 15, 2024
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1 change: 1 addition & 0 deletions lambdalib/iolib/rtl/la_ioclamp.v
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Expand Up @@ -15,6 +15,7 @@ module la_ioclamp
parameter RINGW = 8 // width of io ring
)
(// io pad signals
inout pad, // clamp supply
inout vdd, // core supply
inout vss, // core ground
inout vddio, // io supply
Expand Down
4 changes: 3 additions & 1 deletion lambdalib/iolib/rtl/la_iopoc.v
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Expand Up @@ -12,14 +12,16 @@ module la_iopoc
#(
parameter PROP = "DEFAULT", // cell property
parameter SIDE = "NO", // "NO", "SO", "EA", "WE"
parameter CFGW = 16, // width of core config bus
parameter RINGW = 8 // width of io ring
)
(
inout vdd, // core supply
inout vss, // core ground
inout vddio, // io supply
inout vssio, // io ground
inout [RINGW-1:0] ioring // generic ioring interface
inout [RINGW-1:0] ioring,// generic ioring interface
input [CFGW-1:0] cfg // generic config interface
);

endmodule
1 change: 1 addition & 0 deletions lambdalib/padring/rtl/la_iopadring.vh
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Expand Up @@ -25,3 +25,4 @@ localparam [7:0] LA_VDDA = 8'h14;
localparam [7:0] LA_VSSA = 8'h15;
localparam [7:0] LA_POC = 8'h16;
localparam [7:0] LA_CUT = 8'h17;
localparam [7:0] LA_CLAMP = 8'h18;
18 changes: 17 additions & 1 deletion lambdalib/padring/rtl/la_ioside.v
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Expand Up @@ -195,8 +195,10 @@ module la_ioside
begin : gpoc
la_iopoc #(.SIDE(SIDE),
.PROP(CELLMAP[(i*40+32)+:8]),
.CFGW(CFGW),
.RINGW(RINGW))
i0 (.vss(vss),
i0 (.cfg(cfg[CELLMAP[(i*40)+:8]*CFGW+:CFGW]),
.vss(vss),
.vdd(vdd[CELLMAP[(i*40+24)+:8]]),
.vddio(vddio[CELLMAP[(i*40+24)+:8]]),
.vssio(vssio[CELLMAP[(i*40+24)+:8]]),
Expand All @@ -210,6 +212,7 @@ module la_ioside
.RINGW(RINGW))
i0 (.vss(vss));
end
// LA_VDDIO
if (CELLMAP[(i*40+16)+:8] == LA_VDDIO)
begin : gvddio
la_iovddio #(.SIDE(SIDE),
Expand Down Expand Up @@ -282,6 +285,19 @@ module la_ioside
.vssio(vssio[CELLMAP[(i*40+24)+:8]]),
.ioring(ioring[CELLMAP[(i*40+24)+:8]*RINGW+:RINGW]));
end
// LA_CLAMP
if (CELLMAP[(i*40+16)+:8] == LA_CLAMP)
begin : gclamp
la_iovssa #(.SIDE(SIDE),
.PROP(CELLMAP[(i*40+32)+:8]),
.RINGW(RINGW))
i0 (.pad(pad[CELLMAP[(i*40)+:8]]),
.vss(vss),
.vdd(vdd[CELLMAP[(i*40+24)+:8]]),
.vddio(vddio[CELLMAP[(i*40+24)+:8]]),
.vssio(vssio[CELLMAP[(i*40+24)+:8]]),
.ioring(ioring[CELLMAP[(i*40+24)+:8]*RINGW+:RINGW]));
end
end

endmodule