QoL: Clock polarity after Si53340 is flipped

[MorganTL]

• During the phaser DRTIO port, I experience eem_drtio link issue when using the inverted CK_GTP as the main sys clock.
  • issue disappear after the clock polarity was inverted manually before using it as sys clock (It's a hardware issue in my setup, the cables I used created poor quality clock/data).
• However, I assume it was inverted due to routing issue. I mark this as QoL for now.