Minor Release v2.60.0

Pull Requests Since v2.59.1

Unlabeled

1. #1290 - Adding more line rate support for PGPv4 + GTY+
2. #1291 - Misc. Versal Support
3. #1294 - PGPv4 Dynamic TX/RX Polarity Config
4. #1288 - coaxpress updates
5. #1293 - QsfpCdrDisable.vhd Update & Adding LeapXcvrCdrDisable.vhd
6. #1292 - Additional Error Checking in AXI-Lite Crossbar & globally updated assert severity change from error to failure
7. #1280 - UDP Tx Engine: Fix inferred latch
8. #1289 - TenGigEth Patch for Vivado 2025.1
9. #1283 - Use string enums for different HTSP clock frequency options
10. #1282 - Create dummy register to trick emacs vhdl-update-sensitivity-list
11. #1285 - Signals floating rely on init value
12. #1287 - SugoiAxiLitePixelMatrixConfig: Added function to read programmed pixel
13. #1284 - Digital ASIC Regression Testing
14. #1286 - Fixed AxiLiteToSaci2 addressing

Pull Request Details

UDP Tx Engine: Fix inferred latch

Author:	Larry Ruckman [email protected]
Date:	Mon May 19 09:15:47 2025 -0700
Pull:	#1280 (8 additions, 7 deletions, 1 files changed)
Branch:	slaclab/remove-udp-latch

Notes:

Description

• After a bug fix in ruckus (slaclab/ruckus#347), we discovered this latch in the UDP code, which is bad practice and not allow in the SURF coding style

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Create dummy register to trick emacs vhdl-update-sensitivity-list

Author:	Larry Ruckman [email protected]
Date:	Tue May 20 13:26:00 2025 -0700
Pull:	#1282 (7 additions, 5 deletions, 2 files changed)
Branch:	slaclab/sensitivity-list-fix

Notes:

Description

The emacs update sensitivity list command will now work properly on AxiStreamPacketizer2.vhd

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Use string enums for different HTSP clock frequency options

Author:	Larry Ruckman [email protected]
Date:	Tue Jun 17 10:20:56 2025 -0700
Pull:	#1283 (6 additions, 6 deletions, 2 files changed)
Branch:	slaclab/htsp-dev

Notes:

Description

This is a bit cleaner, and allows for future expansion.

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Digital ASIC Regression Testing

Author:	Larry Ruckman [email protected]
Date:	Fri Jun 20 08:24:46 2025 -0700
Pull:	#1284 (2 additions, 2 deletions, 20 files changed)
Branch:	slaclab/digital-asic-regression-testing

Notes:

Description

• Tested for Synopsis DC and Cadence Genus
• moving this source code to dsp/xilinx
  • Due to cadence not having ieee.fixed_pkg & ieee.fixed_float_types
• bug fix for cadence genus
  • tool complaining about " : Invalid or unsupported VHDL syntax is encountered."

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Signals floating rely on init value

Author:	Larry Ruckman [email protected]
Date:	Sun May 25 07:59:01 2025 -0700
Pull:	#1285 (6 additions, 4 deletions, 1 files changed)
Branch:	slaclab/Pgp4TxLite-bugfix

Notes:

Description

• sync* signals do not get reset/assigned if Synchronizers are bypassed when used in digital ASIC

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Fixed AxiLiteToSaci2 addressing

Author:	Larry Ruckman [email protected]
Date:	Sun Jun 8 11:10:19 2025 -0700
Pull:	#1286 (2 additions, 2 deletions, 1 files changed)
Branch:	slaclab/axilite2saci2-fix

Notes:

Description

Fixed ASIC/chip number in AxiLiteToSaci2

• The masking of the AxiLite Address that was used to derive the ASIC/chip number was off by 2 bits.

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SugoiAxiLitePixelMatrixConfig: Added function to read programmed pixel

Author:	Larry Ruckman [email protected]
Date:	Sun Jun 8 11:04:12 2025 -0700
Pull:	#1287 (6 additions, 0 deletions, 1 files changed)
Branch:	slaclab/sugoi-matrix-config-improve

Notes:

Description

Added a function to read the programmed pixels of the ASICs that use this function.
This is especially useful for SparkPixRT and SparkPixS ASICs where the slow control physical signals have an extra dangling lane inside the ASIC (this makes readsback-verify to fail).

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coaxpress updates

Author:	Larry Ruckman [email protected]
Date:	Fri Jun 20 08:24:59 2025 -0700
Pull:	#1288 (139 additions, 96 deletions, 9 files changed)
Branch:	slaclab/PhantomS641-patch

Notes:

Description

• Serial registers access not availible for PhantomS641
• removing _stop() has there is a corner case bug with memBase removed before this set(0)
• chaning DeviceDiscovery() from cmd to function with a arg for overwritting ConnectionConfigDefault.value()
• adding FW/SW GtRstAll register

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TenGigEth Patch for Vivado 2025.1

Author:	Larry Ruckman [email protected]
Date:	Fri Jun 20 08:25:40 2025 -0700
Pull:	#1289 (13 additions, 0 deletions, 3 files changed)
Branch:	slaclab/gth-10GbE-2025.1-patch

Notes:

Description

• Bug fix for building with Vivado 2025.1
• Here's the error message that this pull request patches ....

The following error(s) were detected during implementation:
ERROR: [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: U_Core/GEN_ETH.U_Rudp/GEN_10G.U_10GigE/GEN_LANE[0].TenGigEthGthUltraScale_Inst/U_TenGigEthGthUltraScaleCore/U0/TenGigEthGthUltraScale156p25MHzCore_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/gt_txd[61]_i_3.
ERROR: [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: 
U_Core/GEN_ETH.U_Rudp/GEN_10G.U_10GigE/GEN_LANE[0].TenGigEthGthUltraScale_Inst/U_TenGigEthGthUltraScaleCore/U0/TenGigEthGthUltraScale156p25MHzCore_core/ten_gig_eth_pcs_pma_inst/G_IS_BASER.ten_gig_eth_pcs_pma_inst/BASER.ten_gig_eth_pcs_pma_inst/gt_txd[61]_i_3.

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Adding more line rate support for PGPv4 + GTY+

Author:	Larry Ruckman [email protected]
Date:	Wed Jun 18 08:12:28 2025 -0700
Pull:	#1290 (6212 additions, 17 deletions, 12 files changed)
Branch:	slaclab/pgp4-17G-dev

Notes:

Description

• adding PGPv4@13G support
  • 13.75Gbps useful link rate as within the 25.78125Gb/s QSFP CDR's link rate margin
• adding PGPv4@17G support
• adding PGPv4@18G support
• adding PGPv4@20G support ... but may not make timing closure
  • Additional work in the AxiStreamDepacketizer2 is required to pipeline the CRC calculation, which is too long of a comb logic chain at 315.2MHz clock

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Misc. Versal Support

Author:	Larry Ruckman [email protected]
Date:	Fri Jun 20 08:25:13 2025 -0700
Pull:	#1291 (540 additions, 7 deletions, 15 files changed)
Branch:	slaclab/Versal-dev

Notes:

Description

• adding ClockManagerVersal.vhd
• reorg of UltraScale+ src code
• clean up assert error msg

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Additional Error Checking in AXI-Lite Crossbar & globally updated assert severity change from error to failure

Author:	Larry Ruckman [email protected]
Date:	Fri Jun 20 08:29:54 2025 -0700
Pull:	#1292 (82 additions, 59 deletions, 33 files changed)
Branch:	slaclab/AxiLiteCrossbar-patch

Notes:

Description

• Do not allow MASTER AXI-Lite configuration that have non-zero within the memory address space region
• In addition, it was discovered that assert severity must be failure (instead of error) to trigger error in cocotb+pytest

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QsfpCdrDisable.vhd Update & Adding LeapXcvrCdrDisable.vhd

Author:	Larry Ruckman [email protected]
Date:	Wed Jun 18 14:56:13 2025 -0700
Pull:	#1293 (218 additions, 2 deletions, 2 files changed)
Branch:	slaclab/leap-cdr-disable

Notes:

Description

• removing unused variable in QsfpCdrDisable.vhd
• adding LeapXcvrCdrDisable.vhd
  • Functionally the same behavior as QsfpCdrDisable but specific to the LEAP transceiver for disabling CDR register in FW (no SW required)

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PGPv4 Dynamic TX/RX Polarity Config

Author:	Larry Ruckman [email protected]
Date:	Fri Jun 20 08:49:03 2025 -0700
Pull:	#1294 (184 additions, 107 deletions, 18 files changed)
Branch:	slaclab/pgp4-dynamic-polarity-config
Issues:	#1294

Notes:

Description

• Previously the RX and TX polarity for the GTs were set by generic during FW build
• This patch will enable us to dynamically change the TX/RX polarities via SW after FW build
• Required for specific situation where disabling a QSFP's CDR causes the serial bit to invert in the QSFP module

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