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jservjserv
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Merge pull request #65 from Risheng1128/pr
Pass several privilege tests and fix RV32I comment
2 parents 5969a17 + 1de60d7 commit b4d8f97

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-36
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4 files changed

+37
-36
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‎README.md

+1-12
Original file line numberDiff line numberDiff line change
@@ -86,19 +86,8 @@ Current progress of this emulator in riscv-arch-test(RV32):
8686
- `Zifencei`: Instruction-Fetch Fence
8787
* Failed Tests
8888
- `privilege`: RISCV Privileged Specification
89-
+ 2 system calls
90-
* `ebreak`
89+
+ 1 system calls
9190
* `ecall`
92-
+ 5 misaligned CB-type instructions
93-
* `misalign-beq`
94-
* `misalign-bge`
95-
* `misalign-bgeu`
96-
* `misalign-blt`
97-
* `misalign-bltu`
98-
+ 1 misaligned CL-type instructions
99-
* `misalign-lw`
100-
+ 1 misaligned CS-type instructions
101-
* `misalign-sw`
10291
* Unsupported tests (runnable but incomplete)
10392
- `F` Standard Extension for Single-Precision Floating-Point
10493

‎src/emulate.c

+29-23
Original file line numberDiff line numberDiff line change
@@ -90,8 +90,8 @@ RV_EXCEPTION_LIST
9090
static inline bool op_load(struct riscv_t *rv, uint32_t insn UNUSED)
9191
{
9292
/* I-type
93-
* 31 26 21 16 11 9 6 0
94-
* [ rd 5][ rs1 5][ immhi 5][ immlo 7][fun3][ opcode 7]
93+
* 31 20 19 15 14 12 11 7 6 0
94+
* | imm[11:0] | rs1 | funct3 | rd | opcode |
9595
*/
9696
const int32_t imm = dec_itype_imm(insn);
9797
const uint32_t rs1 = dec_rs1(insn);
@@ -167,8 +167,8 @@ static inline bool op_misc_mem(struct riscv_t *rv, uint32_t insn UNUSED)
167167
static inline bool op_op_imm(struct riscv_t *rv, uint32_t insn)
168168
{
169169
/* I-type
170-
* 31 26 21 16 11 9 6 0
171-
* [ rd 5][ rs1 5][ immhi 5][ immlo 7][fun3][ opcode 7]
170+
* 31 20 19 15 14 12 11 7 6 0
171+
* | imm[11:0] | rs1 | funct3 | rd | opcode |
172172
*/
173173
const int32_t imm = dec_itype_imm(insn);
174174
const uint32_t rd = dec_rd(insn);
@@ -268,8 +268,8 @@ static inline bool op_op_imm(struct riscv_t *rv, uint32_t insn)
268268
static inline bool op_auipc(struct riscv_t *rv, uint32_t insn)
269269
{
270270
/* U-type
271-
* 31 26 21 16 11 9 6 0
272-
* [ rd 5][ upper immediate 19][ opcode 7]
271+
* 31 12 11 7 6 0
272+
* | imm[31:12] | rd | opcode |
273273
*/
274274
const uint32_t rd = dec_rd(insn);
275275
const uint32_t val = dec_utype_imm(insn) + rv->PC;
@@ -287,7 +287,8 @@ static inline bool op_auipc(struct riscv_t *rv, uint32_t insn)
287287
static inline bool op_store(struct riscv_t *rv, uint32_t insn)
288288
{
289289
/* S-type
290-
* | imm[11:5] | rs2 | rs1 | imm[4:0] | rd | opcode |
290+
* 31 25 24 20 19 15 14 12 11 7 6 0
291+
* | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode |
291292
*/
292293
const int32_t imm = dec_stype_imm(insn);
293294
const uint32_t rs1 = dec_rs1(insn), rs2 = dec_rs2(insn);
@@ -335,8 +336,8 @@ static inline bool op_store(struct riscv_t *rv, uint32_t insn)
335336
static inline bool op_op(struct riscv_t *rv, uint32_t insn)
336337
{
337338
/* R-type
338-
* 31 26 21 16 11 9 6 0
339-
* [ rd 5][ rs1 5][ rs2 5][ funct 10][ opcode 7]
339+
* 31 25 24 20 19 15 14 12 11 7 6 0
340+
* | funct7 | rs2 | rs1 | funct3 | rd | opcode |
340341
*/
341342
const uint32_t rd = dec_rd(insn);
342343
const uint32_t funct3 = dec_funct3(insn);
@@ -496,8 +497,8 @@ static inline bool op_op(struct riscv_t *rv, uint32_t insn)
496497
static inline bool op_lui(struct riscv_t *rv, uint32_t insn)
497498
{
498499
/* U-type
499-
* 31 26 21 16 11 9 6 0
500-
* [ rd 5][ upper immediate 19][ opcode 7]
500+
* 31 12 11 7 6 0
501+
* | imm[31:12] | rd | opcode |
501502
*/
502503
const uint32_t rd = dec_rd(insn);
503504
const uint32_t val = dec_utype_imm(insn);
@@ -517,8 +518,8 @@ static inline bool op_branch(struct riscv_t *rv, uint32_t insn)
517518
const uint32_t pc = rv->PC;
518519

519520
/* B-type
520-
* 31 26 21 16 11 9 6 0
521-
* [ immhi 5][ rs1 5][ rs2 5][ immlo 7][fun3][ opcode 7]
521+
* 31 30 25 24 20 19 15 14 12 11 8 7 6 0
522+
* | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] |opcode|
522523
*/
523524
const uint32_t func3 = dec_funct3(insn);
524525
const int32_t imm = dec_btype_imm(insn);
@@ -586,8 +587,8 @@ static inline bool op_jalr(struct riscv_t *rv, uint32_t insn)
586587
const uint32_t pc = rv->PC;
587588

588589
/* I-type
589-
* 31 26 21 16 11 9 6 0
590-
* [ rd 5][ rs1 5][ immhi 5][ immlo 7][fun3][ opcode 7]
590+
* 31 20 19 15 14 12 11 7 6 0
591+
* | imm[11:0] | rs1 | funct3 | rd | opcode |
591592
*/
592593
const uint32_t rd = dec_rd(insn);
593594
const uint32_t rs1 = dec_rs1(insn);
@@ -627,8 +628,8 @@ static inline bool op_jal(struct riscv_t *rv, uint32_t insn)
627628
const uint32_t pc = rv->PC;
628629

629630
/* J-type
630-
* 31 26 21 16 11 9 6 0
631-
* [ jump target 25][ opcode 7]
631+
* 31 30 21 20 19 12 11 7 6 0
632+
* | imm[20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode |
632633
*/
633634
const uint32_t rd = dec_rd(insn);
634635
const int32_t rel = dec_jtype_imm(insn);
@@ -752,10 +753,15 @@ static uint32_t csr_csrrc(struct riscv_t *rv, uint32_t csr, uint32_t val)
752753
static inline bool op_system(struct riscv_t *rv, uint32_t insn)
753754
{
754755
/* I-type
755-
* 31 26 21 16 11 9 6 0
756-
* [ rd 5][ rs1 5][ immhi 5][ immlo 7][fun3][ opcode 7]
756+
* system instruction
757+
* 31 20 19 15 14 12 11 7 6 0
758+
* | funct12 | rs1 | funct3 | rd | opcode |
759+
*
760+
* csr instruction
761+
* 31 20 19 15 14 12 11 7 6 0
762+
* | csr | rs1 | funct3 | rd | opcode |
757763
*/
758-
const int32_t imm = dec_itype_imm(insn);
764+
const int32_t funct12 = dec_funct12(insn);
759765
const int32_t csr = dec_csr(insn);
760766
const uint32_t funct3 = dec_funct3(insn);
761767
const uint32_t rs1 = dec_rs1(insn);
@@ -764,13 +770,13 @@ static inline bool op_system(struct riscv_t *rv, uint32_t insn)
764770
/* dispatch by func3 field */
765771
switch (funct3) {
766772
case 0:
767-
switch (imm) { /* dispatch from imm field */
768-
case 0: /* ECALL: Environment Call */
773+
switch (funct12) { /* dispatch from imm field */
774+
case 0: /* ECALL: Environment Call */
769775
rv->io.on_ecall(rv);
770776
break;
771777
case 1: /* EBREAK: Environment Break */
772778
rv->io.on_ebreak(rv);
773-
break;
779+
return true;
774780
case 0x002: /* URET: Return from handling an interrupt or exception */
775781
case 0x102: /* SRET */
776782
case 0x202: /* HRET */

‎src/riscv_private.h

+6
Original file line numberDiff line numberDiff line change
@@ -261,6 +261,12 @@ static inline uint32_t dec_r4type_rs3(const uint32_t insn)
261261
return (insn & FR4_RS3) >> 27;
262262
}
263263

264+
/* decode system instruction immediate (same as itype) */
265+
static inline uint32_t dec_funct12(const uint32_t insn)
266+
{
267+
return ((uint32_t)(insn & FI_IMM_11_0)) >> 20;
268+
}
269+
264270
/* decode csr instruction immediate (same as itype, zero extend) */
265271
static inline uint32_t dec_csr(const uint32_t insn)
266272
{

‎tests/arch-test-target/device/rv32i_m/privilege/Makefile.include

+1-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ RUN_TARGET= $(TARGETDIR)/build/rv32emu $(<) \
55

66
RISCV_GCC ?= $(RISCV_PREFIX)gcc
77
RISCV_GCC_OPTS ?= \
8-
-march=rv32gc \
8+
-march=rv32g \
99
-mabi=ilp32 \
1010
-static \
1111
-mcmodel=medany \

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