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Avoid duplications in RISC-V exception handlers #61

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jserv opened this issue Sep 29, 2022 · 0 comments · Fixed by #63
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Avoid duplications in RISC-V exception handlers #61

jserv opened this issue Sep 29, 2022 · 0 comments · Fixed by #63
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jserv commented Sep 29, 2022

Code duplication in the function body of the RISC-V exception handlers might be a maintenance headache. That is, we shall refine these functions in src/emulate.c:

  • rv_except_insn_misaligned
  • rv_except_load_misaligned
  • rv_except_store_misaligned
  • rv_except_illegal_insn
  • rv_except_breakpoint proposed in Implement ebreak properly #60

Code generation using preprocessor macros may be an approach to avoid such duplications.
@Risheng1128 Risheng1128 mentioned this issue Oct 2, 2022
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Risheng1128 added a commit to Risheng1128/rv32emu that referenced this issue Oct 3, 2022
@Risheng1128
Avoid duplications in RISC-V exception handlers
21c09f0 
Use preprocessor to avoid duplications in exception handlers,
and create a list to define the RISC-V exception code.

Close sysprog21#61
@jserv jserv closed this as completed in #63 Oct 3, 2022
vestata pushed a commit to vestata/rv32emu that referenced this issue Jan 24, 2025
@Risheng1128
Avoid duplications in RISC-V exception handlers
d6c8f7c 
Use preprocessor to avoid duplications in exception handlers,
and create a list to define the RISC-V exception code.

Close sysprog21#61
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Avoid duplications in RISC-V exception handlers Risheng1128/rv32emu
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