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Detect NaN in FADD and FSUB #24
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List the difference of the results generated by make arch-test RISCV_DEVICE=F
between the original implementation and the proposed one.
Moved the definition to |
Check CI regressions and attempt to fix. |
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Use "git rebase -i" to squash/rework the commits.
@2011eric, you should mention the results within git commit messages. |
Passed 5 more tests in RV32F, listed in the commit message. |
Read How to Write a Git Commit Message carefully and enforce the rules:
|
I noticed that in the expected output_signature of test |
You can submit issue(s) about floating-point compliance tests if you can recognize. |
I'm not sure if I can state the problem. |
emulate.c
Outdated
@@ -651,7 +653,7 @@ static uint32_t csr_csrrs(struct riscv_t *rv, uint32_t csr, uint32_t val) | |||
if (!c) | |||
return 0; | |||
|
|||
const uint32_t out = *c; | |||
const uint32_t out = (csr == CSR_FFLAGS) ? *c & FFLAG_MASK : *c; |
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Rewrite as following:
uint32_t out = *c;
if (csr == CSR_FFLAGS)
out &= FFLAG_MASK;
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I rewrote the function and also add the same code in csr_csrrw
and csr_csrrc
.
Since FCSR is defined only if ENABLE_RV32F is defined:
static uint32_t *csr_get_ptr(struct riscv_t *rv, uint32_t csr)
{
switch (csr) {
case CSR_CYCLE:
return (uint32_t *) (&rv->csr_cycle) + 0;
case CSR_CYCLEH:
return (uint32_t *) (&rv->csr_cycle) + 1;
case CSR_MSTATUS:
return (uint32_t *) (&rv->csr_mstatus);
case CSR_MTVEC:
return (uint32_t *) (&rv->csr_mtvec);
case CSR_MISA:
return (uint32_t *) (&rv->csr_misa);
case CSR_MSCRATCH:
return (uint32_t *) (&rv->csr_mscratch);
case CSR_MEPC:
return (uint32_t *) (&rv->csr_mepc);
case CSR_MCAUSE:
return (uint32_t *) (&rv->csr_mcause);
case CSR_MTVAL:
return (uint32_t *) (&rv->csr_mtval);
case CSR_MIP:
return (uint32_t *) (&rv->csr_mip);
#ifdef ENABLE_RV32F
case CSR_FFLAGS:
return (uint32_t *) (&rv->csr_fcsr);
case CSR_FCSR:
return (uint32_t *) (&rv->csr_fcsr);
#endif
default:
return NULL;
}
}
Should I also use macro inside csr_csrrs
?
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Should I also use macro inside
csr_csrrs
?
You can do it in another pull request.
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If ENABLE_RV32F
is turned off, build system would complain:
emulate.c: In function ‘csr_csrrw’:
emulate.c:644:16: error: ‘FFLAG_MASK’ undeclared (first use in this function)
644 | out &= FFLAG_MASK;
| ^~~~~~~~~~
emulate.c:644:16: note: each undeclared identifier is reported only once for each function it appears in
emulate.c: In function ‘csr_csrrs’:
emulate.c:661:16: error: ‘FFLAG_MASK’ undeclared (first use in this function)
661 | out &= FFLAG_MASK;
| ^~~~~~~~~~
emulate.c: In function ‘csr_csrrc’:
emulate.c:678:16: error: ‘FFLAG_MASK’ undeclared (first use in this function)
678 | out &= FFLAG_MASK;
| ^~~~~~~~~~
Resolve the above compilation errors.
gcc-9 raises the following warnings:
|
Also, rebase the latest |
Defined several floating-point exceptions and a fflag_mask in riscv_private.h It will now detect invalid_op, overflow, and inexact during execution of FADD and set the corresponding bit in FCSR. Modify csr_get_ptr and csr_csrrs so that insn CSRRS can deal with CSR_FFLAGS. New test passed: fadd_b10-01 fadd_b11-01 fadd_b12-01 fadd_b13-01 fadd_b7-01 Add FFLAG support in csr-relative instuctions
Detect NaN in FADD and FSUB
I used the pattern specified in the RISC-V ISA manual: 0x7fc00000.