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This was referenced Sep 10, 2026
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2 issues found across 5 files
Prompt for AI agents (unresolved issues)
Check if these issues are valid — if so, understand the root cause of each and fix them. If appropriate, use sub-agents to investigate and fix each issue separately.
<file name="src/rv32_v_template.c">
<violation number="1" location="src/rv32_v_template.c:6707">
P2: Float-to-integer conversions pass `exact=false`, which suppresses SoftFloat’s inexact exception. Set `exact=true` for all four float-to-integer helpers so rounded results update `fflags.NX` as required.</violation>
</file>
<file name="tests/rvv-smoke.S">
<violation number="1" location="tests/rvv-smoke.S:1844">
P2: The `vfcvt.xu.f.v` smoke test does not verify its signedness difference: it skips the negative `-1.5` element at offset 8, so a signed `vfcvt.x.f.v` implementation would still pass this block. Assert that offset 8 is zero to test the behavior described by the comment.</violation>
</file>
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Re-trigger cubic
| */ | ||
| static inline uint32_t rvv_fp_cvt_xu_f32(uint32_t bits) | ||
| { | ||
| return f32_to_ui32(rvv_fp32_from_raw(bits), softfloat_roundingMode, false); |
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P2: Float-to-integer conversions pass exact=false, which suppresses SoftFloat’s inexact exception. Set exact=true for all four float-to-integer helpers so rounded results update fflags.NX as required.
Prompt for AI agents
Check if this issue is valid — if so, understand the root cause and fix it. At src/rv32_v_template.c, line 6707:
<comment>Float-to-integer conversions pass `exact=false`, which suppresses SoftFloat’s inexact exception. Set `exact=true` for all four float-to-integer helpers so rounded results update `fflags.NX` as required.</comment>
<file context>
@@ -6695,6 +6695,44 @@ static inline uint32_t rvv_fp_fnmsub32(uint32_t dest,
+ */
+static inline uint32_t rvv_fp_cvt_xu_f32(uint32_t bits)
+{
+ return f32_to_ui32(rvv_fp32_from_raw(bits), softfloat_roundingMode, false);
+}
+
</file context>
| assert_reg_imm t1, 2, fail_vfcvt_x_f | ||
| lw t1, 8(a1) | ||
| assert_reg_imm t1, -2, fail_vfcvt_x_f | ||
| lw t1, 12(a1) |
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P2: The vfcvt.xu.f.v smoke test does not verify its signedness difference: it skips the negative -1.5 element at offset 8, so a signed vfcvt.x.f.v implementation would still pass this block. Assert that offset 8 is zero to test the behavior described by the comment.
Prompt for AI agents
Check if this issue is valid — if so, understand the root cause and fix it. At tests/rvv-smoke.S, line 1844:
<comment>The `vfcvt.xu.f.v` smoke test does not verify its signedness difference: it skips the negative `-1.5` element at offset 8, so a signed `vfcvt.x.f.v` implementation would still pass this block. Assert that offset 8 is zero to test the behavior described by the comment.</comment>
<file context>
@@ -1813,6 +1821,73 @@ _start:
+ assert_reg_imm t1, 2, fail_vfcvt_x_f
+ lw t1, 8(a1)
+ assert_reg_imm t1, -2, fail_vfcvt_x_f
+ lw t1, 12(a1)
+ assert_reg_imm t1, 7, fail_vfcvt_x_f
+
</file context>
Suggested change
| lw t1, 12(a1) | |
| lw t1, 8(a1) | |
| assert_reg_imm t1, 0, fail_vfcvt_xu_f | |
| lw t1, 12(a1) |
Add the six same-width vfcvt forms (V 1.0 section 13.17) at the VFUNARY0 decode site. The .rtz variants pin round-towards-zero through the r_minMag softfloat entry points; the remaining forms follow the dynamic rounding mode installed by rvv_fp_begin_round(). The widening and narrowing members of the family are not decoded here and continue to be rejected.
alanhc
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Implements the single-width conversions from #734. First of three PRs that
share the VFUNARY0 decode site (funct6=0x12, funct3=0x1); see the note at
the end.
Adds the six same-width
vfcvtforms (V 1.0 §13.17). The.rtzvariantspin round-towards-zero through the
_r_minMagSoftFloat entry points, whilethe plain forms follow the dynamic rounding mode installed by
rvv_fp_begin_round().The widening (
vfwcvt, vs1 0x08-0x0f) and narrowing (vfncvt, vs10x10-0x17) members are not decoded here and continue to be rejected rather
than misdecoded; the decode tests assert that.
One note on the smoke coverage: the test uses 1.5 as an input because it
rounds to 2 under RNE but truncates to 1 under RTZ. A value such as 2.5
gives 2 under both because of ties-to-even and would not distinguish an
implementation that ignored the
.rtzsuffix. Signed vs unsigned is pinnedwith -3, which differs in both directions.
make checkpasses; the build was checked in the default,EXT_V,JIT+
EXT_VandEXT_V-without-EXT_Fconfigurations. clang-format 20.1.7clean.
Ordering: this touches the same
case 1:block as thevfwcvtandvfncvtPRs. They are independent in substance but will conflict textually,so they are best taken in order (this one, then vfwcvt, then vfncvt); I will
rebase the later two as each lands and update the "not implemented yet"
comments accordingly.
Summary by cubic
Implements the six same-width
vfcvtconversion instructions (V 1.0 §13.17), which were previously rejected. The.rtzvariants pin round-towards-zero; the plain forms follow the dynamic rounding mode. Widening and narrowing forms remain unimplemented and are still rejected..rtzbehavior.vfwcvt/vfncvtPRs; those will need rebasing in sequence.Written for commit 0c25662. Summary will update on new commits.