Break instruction decoding and emulation into separate stage #93
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This commit breaks RISC-V instruction decoding and emulation into separate
stage, meaning that it is feasible to incorporate further IR optimizations
and JIT code generation.
RISC-V Architecture Test: RV32I/M/C/privilege pass.
This commit introduces the basic block in emulator, meaning that it makes emulator decode and execute numerous instructions at a time. Use hash table and block prediction to manage blocks efficiently. In decode stage, allocate a new block which contains up to 1024 instruction by default, decode the instruction into block until it is full or the latest instruction is a branch instruction and put it into the block map. In execution stage, emulator executes instructions in block. The number of instructions based on the member insn_num in struct block. In particular, when an exception/interrupt occurs, emulator will do the following steps: 1. Execute the exception/interrupt handler that resets a new program counter from the register mtvec and function emulate returns false. 2. Enter to the decode stage again, and create new block based on the new program counter. That is, emulator will stop executing old block and create the new one from new program counter. On the other hand, the file decode.c includes the header file riscv_private.h which includes the gdbstub file. It will make emulator compile failed because the gdbstub is cloned until compiling emulate.c. To resolve this problem, swapping the compile order between emulate.o and decode.o .
Introduce basic block
At present, only object files are tracked at the early build process, which prevents header files from being manipulated properly. We shall add several rules in build system accordingly.
The prefix n_ denotes the number of someting we are referring.
This patch resolves misuse of suffix _t, which should be always treated as the derived types.
In preparation for future enhancements such as computed-goto, there is a need for flexible RISC-V instruction enumeration along with configurable features.
To avoid frequent instruction length checking, move checking into exception handler block. Previously, we had to check the instruction length each time the function 'emulate' was called. Actually, we only need to check it when the exception occurs; otherwise, we can simply set rv->compressed to the appropriate value before running the exception handler. By doing so, we can avoid the overhead of checking instruction length if an exception does not happen.
vestata
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Jan 24, 2025
Break instruction decoding and emulation into separate stage
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wip/instruction-decodebranch breaks RISC-V instruction decoding and emulation into separate stage, meaning that it is feasible to incorporate further IR optimizations and JIT code generation.