prepare for miri supporting the crc intrinsics

test-libz-rs-sys/src/deflate.rs

@@ -2976,7 +2976,7 @@ mod deflate_reset_deterministic {
                 window_bits,
                 8,
                 Z_DEFAULT_STRATEGY,
-                libz_sys::zlibVersion(),
+                libz_rs_sys::zlibVersion(),
                 core::mem::size_of::<z_stream>() as i32,
             );
             assert_eq!(err, Z_OK);
@@ -2996,7 +2996,7 @@ mod deflate_reset_deterministic {
                 window_bits,
                 8,
                 Z_DEFAULT_STRATEGY,
-                libz_sys::zlibVersion(),
+                libz_rs_sys::zlibVersion(),
                 core::mem::size_of::<z_stream>() as i32,
             );
             assert_eq!(err, Z_OK);

test-libz-rs-sys/src/infback.rs

@@ -46,9 +46,14 @@ fn differential_inflate_back<const CHUNK: usize>(input: &[u8]) {
     // Per the documentation, only window_bits 15 is supported.
     let window_bits = 15;
 
-    let ng_out = run_inflate_back_ng::<CHUNK>(input, window_bits);
     let rs_out = run_inflate_back_rs::<CHUNK>(input, window_bits);
 
+    if cfg!(miri) {
+        return;
+    }
+
+    let ng_out = run_inflate_back_ng::<CHUNK>(input, window_bits);
+
     if let (Ok(ng_out), Ok(rs_out)) = (&ng_out, &rs_out) {
         assert_eq!(ng_out.len(), rs_out.len());
 

test-libz-rs-sys/src/inflate.rs

@@ -2201,6 +2201,7 @@ fn issue_232() {
 }
 
 #[test]
+#[cfg_attr(miri, ignore = "slow")]
 fn blow_up_the_stack_1() {
     // requires a sequence of states that would blow up the stack if inflate is not stack safe.
 
@@ -2779,6 +2780,8 @@ fn done_state_returns_stream_end() {
         stream.next_out = out.as_mut_ptr();
 
         assert_eq!(unsafe { inflate(stream, Z_FINISH) }, Z_STREAM_END);
+
+        unsafe { inflateEnd(stream) }
     });
 }
 

zlib-rs/src/crc32/acle.rs

@@ -50,54 +50,65 @@ unsafe fn remainder(mut c: u32, mut buf: &[u8]) -> u32 {
     c
 }
 
+crate::cfg_select! {
+    miri => {
+        use core::arch::aarch64::{__crc32b, __crc32h, __crc32d, __crc32w};
+    }
+    _ => {
+        use asm::{__crc32b, __crc32h, __crc32d, __crc32w};
+    }
+}
+
 // FIXME the intrinsics below are stable since rust 1.80.0: remove these and use the standard
 // library versions once our MSRV reaches that version.
-
-/// CRC32 single round checksum for bytes (8 bits).
-///
-/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)
-#[target_feature(enable = "crc")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-unsafe fn __crc32b(mut crc: u32, data: u8) -> u32 {
-    unsafe {
-        core::arch::asm!("crc32b {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
-        crc
+mod asm {
+
+    /// CRC32 single round checksum for bytes (8 bits).
+    ///
+    /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)
+    #[target_feature(enable = "crc")]
+    #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+    pub unsafe fn __crc32b(mut crc: u32, data: u8) -> u32 {
+        unsafe {
+            core::arch::asm!("crc32b {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
+            crc
+        }
     }
-}
 
-/// CRC32 single round checksum for half words (16 bits).
-///
-/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)
-#[target_feature(enable = "crc")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-unsafe fn __crc32h(mut crc: u32, data: u16) -> u32 {
-    unsafe {
-        core::arch::asm!("crc32h {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
-        crc
+    /// CRC32 single round checksum for half words (16 bits).
+    ///
+    /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)
+    #[target_feature(enable = "crc")]
+    #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+    pub unsafe fn __crc32h(mut crc: u32, data: u16) -> u32 {
+        unsafe {
+            core::arch::asm!("crc32h {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
+            crc
+        }
     }
-}
 
-/// CRC32 single round checksum for words (32 bits).
-///
-/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)
-#[target_feature(enable = "crc")]
-#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
-pub unsafe fn __crc32w(mut crc: u32, data: u32) -> u32 {
-    unsafe {
-        core::arch::asm!("crc32w {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
-        crc
+    /// CRC32 single round checksum for words (32 bits).
+    ///
+    /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)
+    #[target_feature(enable = "crc")]
+    #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+    pub unsafe fn __crc32w(mut crc: u32, data: u32) -> u32 {
+        unsafe {
+            core::arch::asm!("crc32w {crc:w}, {crc:w}, {data:w}", crc = inout(reg) crc, data = in(reg) data);
+            crc
+        }
     }
-}
 
-/// CRC32 single round checksum for double words (64 bits).
-///
-/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)
-#[cfg(target_arch = "aarch64")]
-#[target_feature(enable = "crc")]
-unsafe fn __crc32d(mut crc: u32, data: u64) -> u32 {
-    unsafe {
-        core::arch::asm!("crc32x {crc:w}, {crc:w}, {data:x}", crc = inout(reg) crc, data = in(reg) data);
-        crc
+    /// CRC32 single round checksum for double words (64 bits).
+    ///
+    /// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)
+    #[cfg(target_arch = "aarch64")]
+    #[target_feature(enable = "crc")]
+    pub unsafe fn __crc32d(mut crc: u32, data: u64) -> u32 {
+        unsafe {
+            core::arch::asm!("crc32x {crc:w}, {crc:w}, {data:x}", crc = inout(reg) crc, data = in(reg) data);
+            crc
+        }
     }
 }