[tonyliu312]

Purpose

On SM 12.x (RTX 50-series, NVIDIA GB10 / DGX Spark), the Marlin and Marlin-MoE kernels are currently missing from the compiled _C.so / _moe_C.abi3.so. The driver tries to JIT-promote the 8.0+PTX fallback to SM 12.x, and Marlin-MoE silently produces wrong outputs (V4-Flash MoE decode emits gibberish, while the same model on Hopper produces coherent text).

This PR adds 12.0;12.1 to MARLIN_ARCHS, MARLIN_BF16_ARCHS, and MARLIN_MOE_ARCHS in CMakeLists.txt so native sm_120/sm_121 cubins are emitted.

The fp8 sibling lists (MARLIN_FP8_ARCHS, MARLIN_MOE_FP8_ARCHS) already include 8.9;12.0;12.1, so the precedent and CTK support for SM 12.x in this file is well established. This change just extends the same coverage to the BF16/FP16 paths.

Test Plan

1. Rebuild vLLM on a GB10 / DGX Spark host with TORCH_CUDA_ARCH_LIST=12.1.
2. Verify Marlin-MoE cubins are emitted natively (no PTX JIT fallback).
3. Run V4-Flash decode against the rebuilt wheel; compare output coherence and steady-state throughput against an unpatched baseline.

Test Result

Cubin verification (after rebuild):

$ cuobjdump --list-elf $VLLM/_moe_C.abi3.so | grep -c sm_121
22
$ cuobjdump --list-elf $VLLM/_moe_C.abi3.so | grep -c sm_120
22

(Was 0 on both before this patch — only PTX entries.)

End-to-end model output (V4-Flash, dual DGX Spark, TP=2, single request, max_tokens=80):

	Before	After
Output	gibberish tokens (e.g. repeating punctuation, stale shards)	"Silver light spills down — / A hare pounds rice in the dark, / Watching all the world."
Steady throughput	n/a (corrupt output)	6.28 t/s

Notes

• Hardware tested: GB10 (DGX Spark, sm_121), pair-wise TP=2 over Spectrum-X.
• No code path changes — only CUDA arch list extension. Existing 8.0/9.0 builds are untouched.
• The MoE Marlin kernel itself already builds cleanly for sm_120/sm_121 with CTK 12.6+; this PR just stops excluding those arches from the build matrix.

Related

Relates to ongoing SM 12.x enablement work:

• Refs [New Model] Support DeepseekV4 #40760 (zyongye SM120 attention path)
• Refs [Feat] DeepSeek V4 Rebased  #40860 (ivanium SM120 build matrix tweaks)
• Refs DeepSeek V4 support on SM12x with Triton sparse MLA fallback #40899 (jasl ds4-sm120 — separate scope: DeepSeek-V4 SM12 fused kernels)

Checklist

• Tested on real hardware (GB10 / DGX Spark, sm_121)
• No other paths regressed (sm_80 / sm_90 builds untouched)
• Commit signed-off (DCO)
• CI passes (will be confirmed once submitted)

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[gemini-code-assist]

Code Review

This pull request updates CMakeLists.txt to include SM 12.0 and 12.1 architectures for Marlin FP16, BF16, and MoE kernels to address JIT-related output corruption on Blackwell GPUs. The reviewer recommends also including SM 10.0 and 10.1 architectures, as these data center variants of the Blackwell architecture likely face the same JIT issues and require native compilation for correctness.

[gemini-code-assist]

The PR adds native support for SM 12.x to resolve JIT-related output corruption on Blackwell GPUs. However, it omits SM 10.x (e.g., SM 10.0 for B100/B200), which is the data center variant of the Blackwell architecture. Since vLLM is primarily targeted at data center hardware and the JIT issue likely affects all Blackwell variants, SM 10.0 and 10.1 should also be included in the native architecture list for Marlin FP16 kernels to ensure correctness on these platforms.

  cuda_archs_loose_intersection(MARLIN_ARCHS "8.0+PTX;10.0;10.1;12.0;12.1" "${CUDA_ARCHS}")

[Harry-Chen]

I don't think we are using Marlin kernels on 10.x.

[gemini-code-assist]

Similar to the FP16 path, SM 10.0 and 10.1 should be included here to provide native cubins for data center Blackwell GPUs. These architectures fully support the BF16 MMA instructions used by Marlin, and native compilation is necessary to avoid the JIT-promotion issues described in the PR.

  cuda_archs_loose_intersection(MARLIN_BF16_ARCHS "8.0+PTX;9.0+PTX;10.0;10.1;12.0;12.1" "${CUDA_ARCHS}")

[gemini-code-assist]

For Marlin-MoE, SM 10.0 and 10.1 should also be added to the native architecture list. This ensures that data center Blackwell deployments benefit from the same fix for the "gibberish" output issue identified on SM 12.x hardware.

  cuda_archs_loose_intersection(MARLIN_MOE_ARCHS "8.0+PTX;10.0;10.1;12.0;12.1" "${CUDA_ARCHS}")

[tonyliu312]

Hi @LucasWilkinson @tlrmchlsmth — this is my first vLLM contribution, so the pre-run-check workflow is currently blocked on the first-time-contributor ready label gate (no merged PRs yet on this account, so CI never runs the actual checks).

Would one of you (or anyone else with merge rights) be willing to take a quick look and add the ready label if it looks reasonable? It's a 3-line CMakeLists change adding 12.0;12.1 to MARLIN_ARCHS / MARLIN_BF16_ARCHS / MARLIN_MOE_ARCHS, mirroring the 8.9;12.0;12.1 precedent already in the neighbouring MARLIN_FP8_ARCHS / MARLIN_MOE_FP8_ARCHS lines. Verified end-to-end on GB10 / DGX Spark (sm_121, dual-node TP=2): 22 native sm_121 ELF entries appear in _moe_C.so after rebuild (was 0), and V4-Flash MoE forward output goes from gibberish (PTX-JIT'd cubin from 8.0+PTX) to coherent text.

Happy to address any review feedback. Thanks for your time!

[tonyliu312]

Thanks for the careful review @gemini-code-assist.

Re: extending the arch list to 10.0/10.1 (data-center Blackwell) — the underlying argument generalises (PTX-JIT correctness across major arch jumps is unsafe), but I'd like to keep this PR scoped to changes I can verify on hardware:

• I have GB10 (sm_121) and verified end-to-end: 22 native sm_121 ELF entries appear in _moe_C.so after rebuild (was 0), and V4-Flash MoE forward goes from gibberish to coherent.
• I do not have B100/B200 (sm_100) hardware to verify that the existing sm_80/sm_89/sm_120 Marlin templates even compile cleanly for sm_100, nor that the resulting cubin produces correct outputs there.
• Worth noting that the neighbouring MARLIN_FP8_ARCHS = "8.9;12.0;12.1" doesn't list 10.0 either; sm_100 is currently handled in vLLM by separate dedicated paths (MLA_ARCHS, SCALED_MM_ARCHS, ES_MXFP8_GROUPED_MM_ARCHS, etc., per CMakeLists.txt L498/L522/L776). Adding 10.0/10.1 to MARLIN_* would be a new pattern rather than an extension of the existing 8.9;12.0;12.1 one.

This PR therefore sticks to the extension this is verifiably correct for. A follow-up by someone with sm_100 hardware (or by maintainers via internal CI) would be the right place to add 10.0/10.1 if the Marlin templates do compile cleanly there — happy to file that as a separate issue if useful.

[gemini-code-assist]

Thank you for the detailed explanation and for verifying the changes on the GB10 hardware. That makes perfect sense regarding the scope of this PR—sticking to what is verifiably correct on your hardware is the right approach. I agree that adding support for sm_100 should be handled separately by someone with access to that hardware to ensure proper validation. Your contribution is clear and well-justified. I have no further concerns.

[tonyliu312]

Cross-linking an independent reproduction:

@idonati reported success applying this exact patch on a separate 8× NVIDIA DGX Spark cluster (TP=8, sm_121, RoCE multi-rail) running both DeepSeek-V4-Flash and DeepSeek-V4-Pro: #40899 (comment)

Highlights from their report:

"PR #40923 applied (Marlin MARLIN_ARCHS/MARLIN_BF16_ARCHS/MARLIN_MOE_ARCHS include 12.0;12.1) … Rebuilt vLLM C extensions with TORCH_CUDA_ARCH_LIST="12.0;12.1" (replaces broken "12.0+PTX" which produces no native sm_12x cubins for the MoE Marlin path) … V4-Pro now fires up + serves coherently on the 8-Spark cluster"

Same hardware family (GB10), different cluster size (1× dual-Spark in the original report vs 8× DGX Spark here), same diagnosis, same fix. The change extends the existing MARLIN_FP8_ARCHS = "8.9;12.0;12.1" precedent to the BF16/FP16/MoE entries that were missing it; both reports independently confirm 8.0+PTX JIT alone is not sufficient for sm_120/sm_121 on the Marlin MoE path.

Diff size unchanged (3 lines, CMakeLists.txt only).

[Harry-Chen]

We should use 12.0f wherever possible to reduce cubin size. Same applies to below.

[tonyliu312]

Thanks for the review @Harry-Chen — both points addressed in b7d8baf:

Re: SM 10.x — Confirmed, the diff does not extend to data-center Blackwell. gemini-code-assist suggested adding 10.0/10.1 earlier; I declined for the same reason you mention (Marlin isn't built for the SM10x family). Patch scope stays at consumer Blackwell only.

Re: 12.0f family flag — Applied. Replaced 12.0;12.1 with 12.0f in all three lists (MARLIN_ARCHS, MARLIN_BF16_ARCHS, MARLIN_MOE_ARCHS). This is a strict improvement: produces a single SM12x-family cubin instead of two, and matches the established convention in this file (SCALED_MM_ARCHS, FP4_ARCHS, MLA_ARCHS, CUTLASS_MOE_DATA_ARCHS already use Xf flags).

Re-validated locally on dual DGX Spark TP=2 with V4-Flash + Marlin INT4 path — 12.0f cubin loads correctly on SM121, decode coherent, no regressions.

[Harry-Chen]

@tonyliu312 One thing I forgot to mention -- family specifier is added in CUDA 12.9, and we enable it only with CUDA >= 13.0. For example:

vllm/CMakeLists.txt

Lines 499 to 503 in 19f8624

	if(${CMAKE_CUDA_COMPILER_VERSION} VERSION_GREATER_EQUAL 13.0)
	cuda_archs_loose_intersection(MLA_ARCHS "10.0f;11.0f;12.0f" "${CUDA_ARCHS}")
	else()
	cuda_archs_loose_intersection(MLA_ARCHS "10.0a;10.1a;10.3a;12.0a;12.1a" "${CUDA_ARCHS}")
	endif()

You need to do the same to these MARLIN_XX_ARCHES flags when it involves sm_12x, to avoid compilation issues on CUDA 12.8. You can also do the same to MARLIN_FP8_ARCHS for a unified handling logic for sm_12x.

[tonyliu312]

Right call @Harry-Chen — applied the CUDA 13.0 gate in 06b90bd, mirroring the MLA_ARCHS pattern at L499-503. CUDA 12.8 builds now use 12.0a;12.1a (architecture-specific cubins) instead of the unsupported family flag, while CUDA ≥ 13.0 builds get the single 12.0f family cubin.

Also extended the same gating to MARLIN_FP8_ARCHS per your suggestion (was previously hard-coded to 12.0;12.1 without family-flag option) — gives unified handling across all four MARLIN arch lists.

Full diff is +22/-4 covering MARLIN_ARCHS / MARLIN_BF16_ARCHS / MARLIN_FP8_ARCHS / MARLIN_MOE_ARCHS.

[Harry-Chen]

I've triggered a release pipeline run on your PR. Let's see if it still builds on all platforms: https://buildkite.com/vllm/release-v2/builds/1027

[tonyliu312]

Thanks @Harry-Chen — buildkite/release-v2 ✅, DCO/pre-commit/pre-run-check all green now.

The one outstanding red is buildkite/ci/pr/fusion-e2e-tp2-quick-h100. The diff in this PR is purely CMakeLists.txt arch-list edits gated behind CMAKE_CUDA_COMPILER_VERSION for sm_12x targets, with no changes touching sm_90 (H100) codepaths or fusion logic. That test running on sm_90 hardware should be unaffected. Likely flaky — happy to push an empty commit or signal a re-run if you'd like to retrigger. If you have the buildkite log handy and it's caused by something I'm missing, I'll dig in.

[tonyliu312]

Looked at the buildkite log for the one red mark. The failing test is:

tests/compile/fusion_e2e/test_tp2_ar_rms.py::test_tp2_ar_rms_fp8_fusions
[inductor_partition-quant_fp8-rms_norm-4-TRITON_ATTN-nvidia/Llama-4-Scout-17B-16E-Instruct-FP8-…]

Failure mode: RuntimeError: Engine core initialization failed during model load on H100 (sm_90), TRITON_ATTN backend, FP8-quantized Llama-4-Scout.

This PR's diff is purely CMakeLists.txt arch-list edits for the SM12x family (MARLIN_ARCHS / MARLIN_BF16_ARCHS / MARLIN_FP8_ARCHS / MARLIN_MOE_ARCHS), each guarded behind CMAKE_CUDA_COMPILER_VERSION VERSION_GREATER_EQUAL 13.0. None of these touch sm_90 codepaths or Triton attention. The other 10 fusion tests in the same file passed — only the Llama-4-Scout-FP8 case failed at engine init.

Looks unrelated. Happy to retrigger or push an empty commit if useful, but I don't see a path from this diff to the failure.

[Harry-Chen]

@tonyliu312 It is a flaky test, does not matter. I will request a formal review from a core maintainer.