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[ROCm] Widen AITER fused AR RMSNorm 1-stage gate - #42409

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tjtanaa merged 3 commits into
vllm-project:mainfrom
akii96:rocm-aiter-ar-rms-1stage-gate
May 15, 2026
Merged

tjtanaa merged 3 commits into
vllm-project:mainfrom
akii96:rocm-aiter-ar-rms-1stage-gate

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@akii96

@akii96 akii96 commented May 12, 2026 •

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Purpose

Replace the hardcoded hidden_dim allowlist used for AITER fused allreduce+RMSNorm 1-stage dispatch with the kernel's actual pack-size constraint.

Today, vLLM only enables the AITER 1-stage AR+RMS path for this fixed set of hidden sizes: 512, 1024, 2048, 4096, 7168.

That allowlist is narrower than the kernel constraint and excludes valid model shapes. One concrete example is GPT-OSS, where the relevant hidden size is 2880.

With bf16/fp16 activations, AITER's 1-stage path uses 16-byte vectorized packs:

The predicate mirrors dispatchFusedAllReduceRMSNorm in AITER v0.1.13, the version pinned by docker/Dockerfile.rocm_base:
https://github.com/ROCm/aiter/blob/cdcfa833bdf554ca75594c90dde4316ea9b50199/csrc/include/custom_all_reduce.cuh#L2553-L2554

  • pack_size = 16 / sizeof(T)
  • pack_size = 16 / 2 = 8

For GPT-OSS:

  • hidden_dim = 2880
  • 2880 % 8 == 0
  • 2880 / 8 = 360 <= 1024

So hidden_dim=2880 satisfies the 1-stage kernel constraint, but the previous hardcoded allowlist still forced it away from that path.

This PR changes only the hidden_ok predicate. The existing token_ok and size_ok gates are unchanged, so 1-stage dispatch is still limited by the same token-count, world-size, and message-size checks as before.

The intent is not to add a GPT-OSS-specific special case. Instead, this makes the vLLM dispatch condition match the AITER 1-stage layout rule, allowing any hidden size that satisfies the same pack-size constraint to use the fast path.

Note on concurrency: the 1-stage AITER kernel has a hard token_num <= kMaxBlocks (=80) cap built into its launcher (allreduce_fusion_kernel_1stage_launcher); above that, vLLM correctly falls back to 2-stage via the unchanged token_ok gate. So the PR's perf benefit is largest at low-to-moderate concurrency where decode batches stay under that cap. At very high concurrency (e.g. 32+), the 1-stage path is gated out for most decode steps and the patch is effectively neutral — which is the intended behavior, not a regression.

Test Plan

ROCm MI355X serving validation with openai/gpt-oss-120b, TP=2, AITER unified attention, and fp8 KV cache. Compare median TPOT and output throughput before vs after on the same serving recipe (vllm bench serve, random ISL=1000 / OSL=100, concurrency=8, n=5).

for i in 1 2 3 4 5; do
  echo "=== run $i ==="
  vllm bench serve \
    --backend vllm \
    --dataset-name random \
    --ignore-eos \
    --host localhost \
    --port 8022 \
    --model openai/gpt-oss-120b \
    --ready-check-timeout-sec 6000 \
    --percentile-metrics ttft,tpot,itl,e2el \
    --random-input-len 1000 \
    --random-output-len 100 \
    --max-concurrency 8 \
    --seed 10 \
    --num-prompts 1024 \
    --num-warmups 16
done

Test Result

Test image: vllm/vllm-openai-rocm:nightly-28ee78af543c563a2fbf78829a7688120e4e4eb5
Arch: gfx950 (MI355X)
Model: openai/gpt-oss-120b
Serving setup: MI355X, TP=2, ROCM_AITER_UNIFIED_ATTN, --kv-cache-dtype fp8

Before PR

lm-eval GSM8K:

Tasks Version Filter n-shot Metric Value Stderr
gsm8k 3 flexible-extract 5 exact_match ↑ 0.8931 ± 0.0085
gsm8k 3 strict-match 5 exact_match ↑ 0.1895 ± 0.0108

vllm bench serve (n=5, conc=8):

Metric Value
Median TPOT 4.45 ms
Output token throughput 1430 ± 1 tok/s

After PR

lm-eval GSM8K:

Tasks Version Filter n-shot Metric Value Stderr
gsm8k 3 flexible-extract 5 exact_match ↑ 0.8939 ± 0.0085
gsm8k 3 strict-match 5 exact_match ↑ 0.1797 ± 0.0106

vllm bench serve (n=5, conc=8):

Metric Value
Median TPOT 4.30 ms
Output token throughput 1477 ± 8 tok/s

Delta

Metric Δ
Median TPOT -3.4%
Output token throughput +3.3%

@mergify mergify Bot added the rocm Related to AMD ROCm label May 12, 2026
@github-project-automation github-project-automation Bot moved this to Todo in AMD May 12, 2026

@gemini-code-assist gemini-code-assist Bot left a comment

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Code Review

This pull request updates the logic for determining if a hidden dimension is supported in the ROCm AITER fused all-reduce RMS norm implementation within vllm/_aiter_ops.py. The previous hardcoded list of supported dimensions is replaced with a dynamic check that ensures the hidden dimension is compatible with 16-byte vectorized packs and does not exceed 1024 packs per row. I have no feedback to provide as there were no review comments.

@akii96
akii96 marked this pull request as ready for review May 12, 2026 12:24
@akii96
akii96 requested a review from tjtanaa as a code owner May 12, 2026 12:24

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Claude Code Review

This pull request is from a fork — automated review is disabled. A repository maintainer can comment @claude review to run a one-time review.

@akii96

akii96 commented May 12, 2026

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@gemini-code-assist-user review please with the updated PR body

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Code Review

This pull request updates the _rocm_aiter_fused_allreduce_rmsnorm_impl function in vllm/_aiter_ops.py to generalize the hidden_dim check. Instead of using a hardcoded list of supported dimensions, it now calculates a pack_size based on the input element size and verifies that the hidden_dim is compatible with 16-byte vectorized packs and does not exceed 1024 packs per row. I have no feedback to provide.

@akii96
akii96 force-pushed the rocm-aiter-ar-rms-1stage-gate branch from b163bbc to a47b76c Compare May 12, 2026 13:07
Replace the hardcoded hidden_dim allowlist with aiter's own runtime
predicate (n % pack_size == 0 && n / pack_size <= 1024, where
pack_size = 16 / sizeof(T)), so valid sizes like GPT-OSS hidden_dim=2880
can use the fast path.
Restrict to bf16/fp16, the only dtypes vLLM exercises on this op, so
any unexpected dtype path cleanly falls back to multi-stage. The
predicate is cited against aiter v0.1.13 (the version pinned by
docker/Dockerfile.rocm_base).

Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
@akii96
akii96 force-pushed the rocm-aiter-ar-rms-1stage-gate branch from a47b76c to 47e46fb Compare May 12, 2026 21:05
Move the detailed AITER 1-stage gate citation out of the code so the
implementation keeps only the dispatch predicate.

Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>

@tjtanaa tjtanaa left a comment •

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LGTM. @akii96 Really appreciate for reaching out and also having clear explanation of the situation regarding to technical details of this PR. AITER's internal logic keeps on changing and highlighting his helps expedite the review.

@tjtanaa tjtanaa added the ready ONLY add when PR is ready to merge/full CI is needed label May 15, 2026
@akii96

akii96 commented May 15, 2026 •

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@tjtanaa yeah that needs some work from us still wondering if there is a better longer-term fix but for now this seems to unlock some perf so will proceed with this! Thanks for looking into this!

I think the leftover RTD CI failure just needs a re-run? Can you trigger that please? 😅

@tjtanaa
tjtanaa enabled auto-merge (squash) May 15, 2026 16:03
@tjtanaa
tjtanaa merged commit be7a03e into vllm-project:main May 15, 2026
47 of 48 checks passed
@github-project-automation github-project-automation Bot moved this from Todo to Done in AMD May 15, 2026
@akii96
akii96 deleted the rocm-aiter-ar-rms-1stage-gate branch May 15, 2026 19:15
mfylcek pushed a commit to mfylcek/vllm that referenced this pull request May 19, 2026
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
h1t35h pushed a commit to h1t35h/vllm that referenced this pull request May 21, 2026
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
Liuweixiong0118 pushed a commit to Liuweixiong0118/vllm that referenced this pull request Jun 1, 2026
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
Signed-off-by: Liuweixiong0118 <lwx34158427@gmail.com>
philippesic pushed a commit to philippesic/vllm-semantic-cache that referenced this pull request Jul 19, 2026
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
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