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[ROCm] Widen AITER fused AR RMSNorm 1-stage gate - #42409
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This pull request updates the logic for determining if a hidden dimension is supported in the ROCm AITER fused all-reduce RMS norm implementation within vllm/_aiter_ops.py. The previous hardcoded list of supported dimensions is replaced with a dynamic check that ensures the hidden dimension is compatible with 16-byte vectorized packs and does not exceed 1024 packs per row. I have no feedback to provide as there were no review comments.
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@gemini-code-assist-user review please with the updated PR body |
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This pull request updates the _rocm_aiter_fused_allreduce_rmsnorm_impl function in vllm/_aiter_ops.py to generalize the hidden_dim check. Instead of using a hardcoded list of supported dimensions, it now calculates a pack_size based on the input element size and verifies that the hidden_dim is compatible with 16-byte vectorized packs and does not exceed 1024 packs per row. I have no feedback to provide.
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Replace the hardcoded hidden_dim allowlist with aiter's own runtime predicate (n % pack_size == 0 && n / pack_size <= 1024, where pack_size = 16 / sizeof(T)), so valid sizes like GPT-OSS hidden_dim=2880 can use the fast path. Restrict to bf16/fp16, the only dtypes vLLM exercises on this op, so any unexpected dtype path cleanly falls back to multi-stage. The predicate is cited against aiter v0.1.13 (the version pinned by docker/Dockerfile.rocm_base). Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
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Move the detailed AITER 1-stage gate citation out of the code so the implementation keeps only the dispatch predicate. Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
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LGTM. @akii96 Really appreciate for reaching out and also having clear explanation of the situation regarding to technical details of this PR. AITER's internal logic keeps on changing and highlighting his helps expedite the review.
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@tjtanaa yeah that needs some work from us still wondering if there is a better longer-term fix but for now this seems to unlock some perf so will proceed with this! Thanks for looking into this! I think the leftover RTD CI failure just needs a re-run? Can you trigger that please? 😅 |
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com> Signed-off-by: Liuweixiong0118 <lwx34158427@gmail.com>
Signed-off-by: Aakif Nawaz <aakif.nawaz@amd.com>
Purpose
Replace the hardcoded
hidden_dimallowlist used for AITER fused allreduce+RMSNorm 1-stage dispatch with the kernel's actual pack-size constraint.Today, vLLM only enables the AITER 1-stage AR+RMS path for this fixed set of hidden sizes:
512, 1024, 2048, 4096, 7168.That allowlist is narrower than the kernel constraint and excludes valid model shapes. One concrete example is GPT-OSS, where the relevant hidden size is
2880.With bf16/fp16 activations, AITER's 1-stage path uses 16-byte vectorized packs:
The predicate mirrors
dispatchFusedAllReduceRMSNormin AITER v0.1.13, the version pinned bydocker/Dockerfile.rocm_base:https://github.com/ROCm/aiter/blob/cdcfa833bdf554ca75594c90dde4316ea9b50199/csrc/include/custom_all_reduce.cuh#L2553-L2554
pack_size = 16 / sizeof(T)pack_size = 16 / 2 = 8For GPT-OSS:
hidden_dim = 28802880 % 8 == 02880 / 8 = 360 <= 1024So
hidden_dim=2880satisfies the 1-stage kernel constraint, but the previous hardcoded allowlist still forced it away from that path.This PR changes only the
hidden_okpredicate. The existingtoken_okandsize_okgates are unchanged, so 1-stage dispatch is still limited by the same token-count, world-size, and message-size checks as before.The intent is not to add a GPT-OSS-specific special case. Instead, this makes the vLLM dispatch condition match the AITER 1-stage layout rule, allowing any hidden size that satisfies the same pack-size constraint to use the fast path.
Note on concurrency: the 1-stage AITER kernel has a hard
token_num <= kMaxBlocks(=80) cap built into its launcher (allreduce_fusion_kernel_1stage_launcher); above that, vLLM correctly falls back to 2-stage via the unchangedtoken_okgate. So the PR's perf benefit is largest at low-to-moderate concurrency where decode batches stay under that cap. At very high concurrency (e.g. 32+), the 1-stage path is gated out for most decode steps and the patch is effectively neutral — which is the intended behavior, not a regression.Test Plan
ROCm MI355X serving validation with
openai/gpt-oss-120b, TP=2, AITER unified attention, and fp8 KV cache. Compare median TPOT and output throughput before vs after on the same serving recipe (vllm bench serve, random ISL=1000 / OSL=100, concurrency=8, n=5).Test Result
Test image:
vllm/vllm-openai-rocm:nightly-28ee78af543c563a2fbf78829a7688120e4e4eb5Arch: gfx950 (MI355X)
Model:
openai/gpt-oss-120bServing setup: MI355X, TP=2,
ROCM_AITER_UNIFIED_ATTN,--kv-cache-dtype fp8Before PR
lm-evalGSM8K:vllm bench serve(n=5, conc=8):After PR
lm-evalGSM8K:vllm bench serve(n=5, conc=8):Delta