[xijiaat]

Purpose

Fixes #50714. Allow TP1 DeepSeek-V4-Flash NIXL P/D engines to initialize with mixed-granularity packed MLA caches, without disabling block-size synchronization for ordinary caches.

HMA puts the minimum cache-group block size into the global cache config. For this model it is 4, while attention kernels require 256. These groups count different units: compressor state and compressed attention KV. Requiring a common kernel block size from that global minimum raises ValueError: No common block size for 4 before NIXL registration. Setting --block-size 256 does not fix the later HMA rewrite.

Design And Compatibility

• Reuse the existing whole-storage-row transfer for mixed-block-size, block-outermost MLA allocations. Keep their scheduler-owned blocks intact instead of virtually splitting them using the global minimum.
• Restrict this branch to MLA-only specs, device buffers, PP/PCP/DCP=1, and consistent declared strides. Validate actual shared storage and whole-row coverage before registration, and matching P/D block geometry before accepting a peer.
• Ordinary caches, uniform-block MLA, MLA/Mamba, host-staged buffers and other excluded configurations retain the existing kernel block-size selection and virtual splitting. Model computation, scheduling policy and NIXL wire fields are unchanged.

This replaces the earlier broad block_stride > 0 guard: a positive stride alone no longer identifies packed storage on main. It fixes this initialization path, not general heterogeneous block-size support. Different TP sizes are not rejected solely because TP differs, but actual heterogeneous-TP transfer remains unverified.

Related work: #49845 selects kernel block sizes before the HMA rewrite; #50499 addresses packed pipeline-parallel push routing; #53780 adds general per-region transfer geometry. This PR is the narrower post-HMA initialization fix and does not add their routing or metadata changes.

Validation

Rebase validation (2026-09-20)

Rebased onto main 1c3ef2ad4. The original initialization failure still reproduces on this base; the merged per-region geometry work does not remove the post-HMA block-size synchronization failure.

Updated the test fixtures for upstream transfer-rank and layer-routing fields. Also explicitly retained whole-row descriptors for the validated mixed-granularity packed MLA branch: upstream now allows contiguous member pages to use separate strided regions, so skipping block-size synchronization alone no longer preserves this PR's whole-row transfer invariant. Other registration paths retain main's behavior.

• 28 source-isolated CPU checks passed using real CPU tensor views and mocked NIXL boundaries. The unmodified main negative control still reproduced No common block size for 4.
• Ruff check/format, Python compilation and diff checks passed.
• Full pytest collection was blocked by missing tblib. Full pre-commit was not rerun; the individual checks above were executed directly.
• GPU/NIXL serving tests were not rerun after this rebase. The results below are from the earlier validation against 8369affa5, not the current base. The isolated CPU checks do not replace full pytest or native transport validation.

Original validation

Tested against main 8369affa5, using deepseek-ai/DeepSeek-V4-Flash-0731 and two isolated B300 GPUs, one per TP1 engine in a single Pod. The same model snapshot and launch arguments were used before/after; only base_worker.py was replaced for the serving check.

Check	Result
Stock main startup	Reproduced No common block size for 4
Patched TP1 producer + consumer	Both healthy; NIXL KV transfer succeeded
Four existing CPU-marked NIXL test suites	307 passed, 152 deselected
Serving smoke checks	8/8 expected arithmetic answers, including streaming/nonstreaming, C4 and post-cancel recovery
Stream/nonstream disconnect	Both requests aborted in engine logs; running/waiting returned to zero
Bounded long-request check	24/24 completed: 65,536 input / 1,024 output tokens, C8 x 3 rounds; no reported NIXL transfer failures

The regression tests cover whole-row descriptors and bounds, preservation of ordinary 512-to-256 splitting, invalid runtime views and incompatible peer geometry. The remote-TP parameters exercise metadata validation, not end-to-end heterogeneous TP.

Local Ruff check/format and SPDX checks passed. The full pre-commit invocation did not complete: hook-repository downloads were stopped after several minutes. It is not included in the passed checks above.

These are serving correctness checks, not a model-accuracy benchmark. This run used eager execution and UCX_TLS=tcp,cuda_copy; no NVLink or performance improvement is claimed.

Test commands and TP1 startup reproduction

In the vLLM test environment, from the repository root:

OMP_NUM_THREADS=4 OPENBLAS_NUM_THREADS=4 .venv/bin/python -m pytest \
  tests/v1/kv_connector/unit/test_nixl_desc_geometry.py \
  tests/v1/kv_connector/unit/test_nixl_connector_hma.py \
  tests/v1/kv_connector/unit/test_nixl_connector.py \
  tests/v1/kv_connector/unit/test_nixl_push_connector.py \
  -m cpu_test -q

The isolated Pod used /work/venv/bin/python for this environment. Actual output:

307 passed, 152 deselected, 14 warnings in 92.63s (0:01:32)

Run one role in each of two containers sharing a Pod network, with one distinct GPU allocated to each. Set ROLE=prefill or ROLE=decode, and POD_IP to that Pod's IP. Use the same model revision on both ends. This is the serving command used, with the local model-cache path replaced by its public model ID and revision:

export OMP_NUM_THREADS=4 MKL_NUM_THREADS=4 OPENBLAS_NUM_THREADS=4
export PYTHONHASHSEED=0 VLLM_LOG_STATS_INTERVAL=1 UCX_TLS=tcp,cuda_copy
export VLLM_NIXL_SIDE_CHANNEL_HOST="${POD_IP:?Set the Pod IP}"
case "${ROLE:?Set prefill or decode}" in
  prefill) PORT=18000; KVROLE=kv_producer
           export VLLM_NIXL_SIDE_CHANNEL_PORT=18100 ;;
  decode)  PORT=18001; KVROLE=kv_consumer
           export VLLM_NIXL_SIDE_CHANNEL_PORT=18101 ;;
  *) exit 1 ;;
esac

.venv/bin/python -m vllm.entrypoints.openai.api_server \
  --model deepseek-ai/DeepSeek-V4-Flash-0731 \
  --revision 7872f01b1d1fe23eabc4c98b48bffcef5a386062 \
  --served-model-name deepseek-ai/DeepSeek-V4-Flash-0731 \
  --trust-remote-code --tensor-parallel-size 1 \
  --host 0.0.0.0 --port "$PORT" \
  --tokenizer-mode deepseek_v4 --tool-call-parser deepseek_v4 \
  --enable-auto-tool-choice --reasoning-parser deepseek_v4 \
  --kv-cache-dtype fp8 --gpu-memory-utilization 0.7 \
  --max-model-len 131072 --max-num-batched-tokens 8192 --max-num-seqs 8 \
  --enable-prefix-caching --enable-chunked-prefill \
  --no-disable-hybrid-kv-cache-manager \
  --enable-expert-parallel --moe-backend deep_gemm_mega_moe \
  --attention-config '{"use_fp4_indexer_cache":true}' \
  --enable-prompt-tokens-details --enable-request-id-headers --enable-log-requests \
  --kv-transfer-config "{\"kv_connector\":\"NixlConnector\",\"kv_role\":\"$KVROLE\",\"kv_buffer_device\":\"cuda\",\"kv_connector_extra_config\":{\"backends\":[\"UCX\"],\"num_threads\":8}}" \
  --enforce-eager --seed 2026

Stock main fails in _sync_block_size_with_kernel(). With this change, both engines initialize and expose /health. The serving checks then sent a max_tokens=1, do_remote_decode=true prefill request and forwarded its returned kv_transfer_params with the original request to decode. Successful decode-side cached tokens were treated as transferred KV, not as prefill prefix-cache hits.

AI Assistance

The submitter supplied the failure case, deployment constraints and test requirements, directed the design and isolated B300 validation, and authorized this update. AI assistance was used for implementation, tests, review and documentation. The human submitter remains responsible for reviewing and defending the change.

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🚀

[ovidiusm]

Hi, are you still working on this? Also, have you considered heterogeneous setup (TP different for P and D)?

[coderabbitai]

No actionable comments were generated in the recent review. 🎉

ℹ️ Recent review info

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📒 Files selected for processing (3)

• tests/v1/kv_connector/unit/test_nixl_desc_geometry.py
• tests/v1/kv_connector/unit/test_nixl_push_connector.py
• vllm/distributed/kv_transfer/kv_connector/v1/nixl/base_worker.py

Included review availability: Your plan provides up to 10 included reviews per hour; 9 remain after this review.

---

Walkthrough

NIXL now detects packed MLA caches and transfers complete scheduler blocks without kernel block-size reconciliation. Non-packed paths retain existing splitting. Registration rejects non-shared cache views and peers with incompatible packed block geometry.

Changes

Packed MLA geometry handling

Layer / File(s)	Summary
Packed MLA detection and registration vllm/distributed/kv_transfer/kv_connector/v1/nixl/base_worker.py, tests/v1/kv_connector/unit/test_nixl_desc_geometry.py, tests/v1/kv_connector/unit/test_nixl_push_connector.py	Packed MLA allocations keep scheduler block geometry and register whole-block regions. Non-packed cases continue to split blocks at the kernel size. Test fixtures initialize and validate the packed-transfer flag.
Packed cache and peer validation vllm/distributed/kv_transfer/kv_connector/v1/nixl/base_worker.py, tests/v1/kv_connector/unit/test_nixl_desc_geometry.py	Packed registration requires shared whole-block cache views. Remote peers must match local block size, layout, block lengths, strides, and physical-to-logical block ratio.

Estimated code review effort: 3 (Moderate) | ~20 minutes

Suggested reviewers: lucaswilkinson, njhill

Merge Risk: ⚪ Minimal · up to 9219a

This change enables complete packed MLA cache-slab transfers while retaining existing block splitting for excluded cache layouts and rejecting incompatible local or peer geometry. The covered validations and regression cases leave no current merge-blocking risk.

🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 33.33% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 12 functions across 3 files.	Write docstrings for the functions missing them to satisfy the coverage threshold.

✅ Passed checks (4 passed)

Check name	Status	Explanation
Linked Issues check	✅ Passed	The changes address issue #50714 by preserving scheduler block geometry for validated packed MLA caches, skipping incompatible kernel block-size synchronization, validating storage and peer geometry, …
Out of Scope Changes check	✅ Passed	The implementation and tests stay within the linked issue scope. They cover packed MLA geometry, validation, peer compatibility, and regression behavior without adding unrelated routing or general het…
Title check	✅ Passed	The title clearly and concisely describes the primary change: preserving block geometry for packed MLA caches in NIXL.
Description check	✅ Passed	The description directly explains the initialization failure, the packed MLA geometry fix, compatibility constraints, regression coverage, and validation results.

✨ Finishing Touches 💡 1

🛠️ Fix failing CI checks 💡

• Create stacked PR
• Commit on current branch

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[mergify]

Documentation preview: https://vllm--50717.org.readthedocs.build/en/50717/

[claude]

Claude Code Review

This pull request is from a fork — automated review is disabled. A repository maintainer can comment @claude review to run a one-time review.

[xijiaat]

Thanks @ovidiusm for following up. I have updated this PR against main and validated TP1 P/D startup and transfer on two isolated B300 GPUs.

The fix now preserves whole scheduler-owned rows only for validated mixed-granularity packed MLA storage. Ordinary kernel block-size synchronization and splitting remain unchanged. The CPU-marked NIXL suites passed (307 tests), and streaming/nonstreaming generation, disconnect cleanup and subsequent requests worked. The PR description includes the rationale, scope and reproduction commands.

Regarding heterogeneous TP: the new guard checks physical P/D block geometry rather than requiring equal TP sizes. Metadata validation is covered, but I have not run an end-to-end heterogeneous-TP configuration, so I am not claiming that validation here.

Are there specific heterogeneous P/D TP combinations or additional compatibility checks you would like me to cover?

@ovidiusm @zixi-qi, could you please review this initialization change and its compatibility boundaries when you have time? It reuses packed whole-row transfer rather than changing the transfer protocol. Thank you.

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @xijiaat.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

[xijiaat]

Hi @sangstar @orozery @NickLucche, when you have time, could you please review this PR and let me know what changes or additional validation are needed?

The immediate goal is to unblock homogeneous TP1 P/D with packed MLA caches. I also see the new rebase notice; guidance on how this approach should fit with the ongoing per-region transfer geometry work would help me update it appropriately.

Thank you for your time!

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @xijiaat.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @xijiaat.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

[xijiaat]

Hi @ApostaC @orozery @ivanium @NickLucche @xuechendi, thanks for taking a look. I've rebased this PR onto current main and resolved the conflicts.

The original No common block size for 4 failure still reproduces on main. I also adapted the packed-MLA descriptor branch to preserve whole-row transfers after upstream's per-page registration changes, while keeping other layouts unchanged.

28 source-isolated CPU regression checks pass, along with Ruff and compilation checks. Full pytest collection is blocked by missing tblib locally; GPU/NIXL serving was not rerun for this rebase. The PR description separates this validation from the earlier B300 results.

Could you review whether this scoped approach fits the current NIXL geometry design, and let me know what else needs changing? Thank you.

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @xijiaat.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork