Skip to content

Conversation

@dgarske
Copy link
Contributor

@dgarske dgarske commented Dec 6, 2025

Summary

This PR adds full support for the Microchip PolarFire SoC (MPFS250T) secure boot target, along with a refactoring of GPT (GUID Partition Table) code to make it reusable across multiple architectures.

Key Changes

1. New Platform: Microchip PolarFire SoC (MPFS250)

  • Architecture: RISC-V 64-bit (rv64imac) with five-core CPU cluster (1× E51 monitor core + 4× U54 application cores)
  • New HAL files:
    • hal/mpfs250.c - Hardware abstraction layer implementation (UART and uSD)
    • hal/mpfs250.h - Register definitions and hardware interfaces
    • hal/mpfs250.ld - Linker script for the platform
    • hal/mpfs.dts / hal/mpfs.dtb - Device tree source and binary
    • hal/mpfs.yaml - HSS payload generator configuration
  • New boot files:
    • src/boot_riscv64.c - RISC-V 64-bit boot logic
    • src/boot_riscv64_start.S - Assembly startup code
    • src/vector_riscv64.S - Interrupt vector table
  • Test application: test-app/app_mpfs250.c with linker script
  • Example configuration: config/examples/polarfire_mpfs250.config

2. GPT Refactoring for Cross-Platform Use

Refactored the x86-specific GPT code into a generic, reusable implementation:

  • New generic GPT module: src/gpt.c + include/gpt.h - Platform-independent GPT parsing
  • Disk abstraction: include/disk.h - Common disk interface definitions
  • Renamed: src/x86/gpt.csrc/x86/disk.c (now contains x86-specific disk operations)
  • Enhanced update_disk.c: Updated to work with the generic GPT interface for non-x86 targets

3. Build & CI Updates

  • Added MPFS250 to test-configs.yml workflow for automated build testing
  • Updated arch.mk with RISCV64 architecture support and MPFS250 target rules
  • Tool Makefile updates for cross-compilation compatibility

Testing

  • Build tested with example configuration
  • Added to CI build test matrix

Documentation

Added comprehensive documentation in docs/Targets.md covering:

  • Feature overview
  • Build instructions
  • HSS payload generation
  • Flashing procedures (eMMC/SD via USB-DMSC, eNVM)
  • OpenOCD debugging setup

Future Work (documented)

  1. Full HSS replacement support using wolfBoot
  2. eMMC and QSPI NOR flash driver implementations

@dgarske dgarske self-assigned this Dec 6, 2025
@dgarske dgarske force-pushed the polarfire_soc branch 9 times, most recently from 7acaf16 to f2810fb Compare December 8, 2025 23:55
@dgarske dgarske marked this pull request as ready for review December 8, 2025 23:55
@dgarske dgarske force-pushed the polarfire_soc branch 9 times, most recently from 4a9fd1c to e4bc41b Compare December 9, 2025 23:37
@dgarske dgarske force-pushed the polarfire_soc branch 3 times, most recently from 6a7be50 to 1606e3d Compare December 13, 2025 01:11
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant