DRM :ade : add cmd file function

arch/arm64/boot/dts/hi6220.dtsi

@@ -692,6 +692,7 @@
 				      <0x0 0xf4410000 0x0 0x1000>;
 				reg-names = "ade_base",
 					    "media_base";
+				interrupts = <0 114 0x4>;
 				clocks = <&clock_media HI6220_ADE_CORE>,
 					 <&clock_media HI6220_CODEC_JPEG>,
 					 <&clock_media HI6220_ADE_PIX_SRC>,

arch/arm64/configs/defconfig

@@ -381,3 +381,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=m
 CONFIG_COMPAT_BINFMT_ELF=y
 CONFIG_COMPAT=y
 CONFIG_SYSVIPC_COMPAT=y
+
+CONFIG_ION_HISI=y
+CONFIG_ION=y
+CONFIG_ANDROID=y

drivers/gpu/drm/hisilicon/Makefile

@@ -1,8 +1,10 @@
+ccflags-y += -I$(srctree)/drivers/staging/android
 hisi-drm-y := hisi_drm_drv.o \
 	      hisi_drm_ade.o \
 	      hisi_drm_dsi.o \
 	      hisi_drm_fb.o \
-	      hisi_mipi_reg.o
+	      hisi_mipi_reg.o \
+	      hisi_ade_cmdqueue.o
 
 obj-$(CONFIG_DRM_HISI)	+= hisi-drm.o
 obj-$(CONFIG_DRM_HISI_FBDEV) += hisi_drm_fbdev.o

drivers/gpu/drm/hisilicon/hisi_ade_cmdqueue.c

@@ -0,0 +1,145 @@
+/* Copyright (c) 2008-2010, Hisilicon Tech. Co., Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+
+#include <linux/bitops.h>
+#include "hisi_ade_cmdqueue.h"
+#include <linux/fs.h>
+
+#define  ADE_INVAL_REG      (0xffff)
+
+struct write_cmd_head  wr_cmd;
+
+/* BOARD TYPE */
+enum {
+    ASIC_BOARD = 0,
+    SFT_BOARD  = 1,
+};
+
+/********** ADE Register Union Struct ***********/
+// Define the union U_RD_CH1_PE
+union U_RD_CH1_PE {
+    // Define the struct bits
+    struct
+    {
+        unsigned int    rd_ch1_qos            : 4   ; // [3..0] 
+        unsigned int    rd_ch1_qos_sec        : 4   ; // [7..4] 
+        unsigned int    rd_ch1_qos_thd        : 4   ; // [11..8] 
+        unsigned int    rd_ch1_qos_cfg        : 1   ; // [12] 
+        unsigned int    Reserved_77           : 11  ; // [23..13] 
+        unsigned int    rd_ch1_min_burst_len  : 4   ; // [27..24] 
+        unsigned int    Reserved_76           : 4   ; // [31..28] 
+    } bits;
+
+    // Define an unsigned member
+    unsigned int    u32;
+
+} ;
+
+void ade_cmdq_wr_eof_cmd(void *cmdbuff_vaddr, u32 *cmd_len)
+{
+    NULL_EOF_CMD  eof_cmd;
+    NULL_EOF_CMD  null_cmd;
+    u32 align_count = 0;
+    unsigned   i = 0;
+
+    eof_cmd.ul32 = 0;
+    eof_cmd.bits.cmd_type = ADE_CMD_TYPE_EOF;
+
+    null_cmd.ul32 = 0;
+    null_cmd.bits.cmd_type = ADE_CMD_TYPE_NULL;
+
+    align_count = (*cmd_len + sizeof(eof_cmd.ul32)) % ADE_CMD_ALIGN_BYTE_LEN ;
+    if (align_count != 0) {
+        /* align up to 16*4 byte */
+        align_count = (((*cmd_len / ADE_CMD_ALIGN_BYTE_LEN + 1) * ADE_CMD_ALIGN_BYTE_LEN) - sizeof(eof_cmd.ul32) - *cmd_len) / 4;
+        for (i = 0; i < align_count; i++) {
+            memcpy((char*)cmdbuff_vaddr + *cmd_len, &null_cmd, sizeof(null_cmd.ul32));
+            *cmd_len += sizeof(null_cmd.ul32);
+        }
+    }
+
+    memcpy((char*)cmdbuff_vaddr + *cmd_len, &eof_cmd.ul32, sizeof(eof_cmd.ul32));
+    *cmd_len += sizeof(eof_cmd.ul32);
+
+}
+
+void ade_cmdq_wr_cmd2buff(void* cmdbuff_vaddr, u32 *cmd_len)
+{
+    u32   wr_cmd_len = 0;
+
+    if (wr_cmd.cmd_head.bits.first_reg_offset == ADE_INVAL_REG) {
+        return;
+    }
+
+    wr_cmd_len = sizeof(wr_cmd.cmd_head.ul32) * (wr_cmd.cmd_head.bits.arg_len + 1);
+    wr_cmd.cmd_head.bits.arg_len -= 1;
+
+    memcpy((char*)cmdbuff_vaddr + *cmd_len, &wr_cmd, wr_cmd_len);
+    *cmd_len += wr_cmd_len;
+
+    wr_cmd.cmd_head.bits.cmd_type = ADE_CMD_TYPE_WRITE;
+    wr_cmd.cmd_head.bits.arg_len  = 0;
+    wr_cmd.cmd_head.bits.first_reg_offset = ADE_INVAL_REG;
+}
+
+/************************* RDMA *********************************/
+inline void ade_cmdq_wr_cmd(u32 reg_addr, u32 val)
+{
+    u32 last_reg;
+
+    if (reg_addr == ADE_INVAL_REG) {
+        return;
+    }
+
+    last_reg = wr_cmd.cmd_head.bits.arg_len * 4 + wr_cmd.cmd_head.bits.first_reg_offset;
+
+    wr_cmd.cmd_head.bits.cmd_type = ADE_CMD_TYPE_WRITE;
+    if ((last_reg == reg_addr) && (wr_cmd.cmd_head.bits.arg_len < ADE_CMD_WITE_REG_MAX)) {
+        wr_cmd.reg_val[wr_cmd.cmd_head.bits.arg_len] = val;
+        wr_cmd.cmd_head.bits.arg_len++;
+    } else {
+        wr_cmd.cmd_head.bits.first_reg_offset = reg_addr;
+        wr_cmd.cmd_head.bits.arg_len = 1;
+        wr_cmd.reg_val[0] = val;
+    }
+}
+
+void ade_cmdq_wr_rdma_pe_cmd(u32 reg_addr, u32 ch_type, u32 rotation)
+{
+    volatile union U_RD_CH1_PE rdma_pe;
+
+    rdma_pe.u32 = 0;
+
+    /* the min burst len is 16 when no rotation, is 4 when have online rotation */
+    rdma_pe.bits.rd_ch1_min_burst_len = 0xf;
+    if (OVERLAY_PIPE_TYPE_ONLINE == ch_type) {
+	    rdma_pe.bits.rd_ch1_qos = 4;
+	    if (rotation != ADE_ROT_NOP) {
+            rdma_pe.bits.rd_ch1_min_burst_len = 0x3;
+	    }
+    } else {
+	    rdma_pe.bits.rd_ch1_qos = 2;
+    }
+#if 0
+    if (SFT_BOARD == fb_get_board_type()) {
+        rdma_pe.bits.rd_ch1_min_burst_len = 0x3;
+    }
+#endif
+    ade_cmdq_wr_cmd(reg_addr, rdma_pe.u32);
+
+}

drivers/gpu/drm/hisilicon/hisi_ade_cmdqueue.h

@@ -0,0 +1,102 @@
+/* Copyright (c) 2008-2011, Hisilicon Tech. Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *	 * Redistributions of source code must retain the above copyright
+ *	   notice, this list of conditions and the following disclaimer.
+ *	 * Redistributions in binary form must reproduce the above
+ *	   copyright notice, this list of conditions and the following
+ *	   disclaimer in the documentation and/or other materials provided
+ *	   with the distribution.
+ *	 * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *	   contributors may be used to endorse or promote products derived
+ *	   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ADE_CMDQUEUE_H__
+#define __ADE_CMDQUEUE_H__
+
+#define ADE_CMD_WITE_REG_MAX            (128) 
+#define ADE_CMD_ALIGN_BYTE_LEN           (64)   /* 16 * 4, 16 words */
+/*************************enum***************************/
+enum {
+	ADE_CMD_TYPE_NULL  = 0x0,
+	ADE_CMD_TYPE_WRITE = 0x1,
+	ADE_CMD_TYPE_READ  = 0x2,
+	ADE_CMD_TYPE_WAIT  = 0x3,
+	ADE_CMD_TYPE_EOF   = 0x4,
+	ADE_CMD_TYPE_INVAL
+}; 
+
+enum ADE_ROT{
+	ADE_ROT_NOP = 0,
+	ADE_ROT_90,
+	ADE_ROT_180,
+	ADE_ROT_270,
+    ADE_ROT_H_MIRROR,
+    ADE_ROT_V_MIRROR,
+    ADE_ROT_90_H_MIRROR,
+    ADE_ROT_90_V_MIRROR,
+    ADE_ROT_INVALID
+};
+enum OVERLAY_PIPE_NUM{
+	OVERLAY_PIPE_ADE_CH1 = 0,
+	OVERLAY_PIPE_ADE_CH2,
+	OVERLAY_PIPE_ADE_CH3,
+	OVERLAY_PIPE_ADE_CH4,
+	OVERLAY_PIPE_ADE_CH5,
+	OVERLAY_PIPE_ADE_CH6,
+	OVERLAY_PIPE_ADE_DISP,
+
+	OVERLAY_PIPE_ADE_MAX
+};
+
+enum OVERLAY_PIPE_TYPE {
+    OVERLAY_PIPE_TYPE_ONLINE = 0,
+    OVERLAY_PIPE_TYPE_OFFLINE,
+    OVERLAY_PIPE_TYPE_COPYBIT,
+    OVERLAY_PIPE_TYPE_DISPLAY,
+    OVERLAY_PIPE_TYPE_INVAL
+};
+
+typedef union {
+	struct {
+		u32     first_reg_offset : 16;
+		u32     arg_len  : 8;
+		u32     cmd_type : 8;
+		}bits;
+	u32     ul32;
+}WRITE_CMD_HEAD;
+
+typedef union {
+    struct {
+        u32     reserved : 24;
+        u32     cmd_type : 8;
+    }bits;
+    u32     ul32;
+}NULL_EOF_CMD;
+
+struct write_cmd_head {
+	WRITE_CMD_HEAD   cmd_head;
+	u32              reg_val[ADE_CMD_WITE_REG_MAX];
+	}; 
+
+extern void ade_cmdq_wr_rdma_pe_cmd(u32 reg_addr, u32 ch_type, u32 rotation);
+extern void ade_cmdq_wr_cmd(u32 reg_addr, u32 val);
+extern void ade_cmdq_wr_cmd2buff(void *cmdbuff_vaddr, u32 *cmd_len);
+extern void ade_cmdq_wr_eof_cmd(void *cmdbuff_vaddr, u32 *cmd_len); 
+#endif  /*  ADE_CMDQUEUE_H  */