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zenit-abh/README.md

Hi there , I'm Rishabh Upadhyay currently pursuing B.Tech in Electronics and Communication Engineering from Institute of Technology , Guru Ghasidas Vishwavidyalaya(Central University)👋

  • 🔭 I’m currently working on Verilog programs
  • 🌱 I’m currently learning Verilog and Vivado
  • 👯 I’m looking to collaborate on OpenSourced projects on Verilog and FPGA design.
  • 🤔 I’m looking for help with FPGA design codes
  • 💬 Ask me about Verilog/Digital Circuits
  • 📫 How to reach me: Instagram , LinkedIn , Facebook , Gmail
  • 😄 Pronouns: Learner, Enthusiat
  • ⚡ Fun fact: Peanuts aren’t technically nuts

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