Description
Describe the bug
Hello all,
I am using a peripheral which have an internal FIFO. From that peripheral, I receive the interrupt when fifo is full. I received the interrupt every 160ms and read 360 bytes of data. It uses a fixed register read/write cycle every interrupt for fifo read. This process is successful over the longtime. After some random point of time SPI driver sent the wrong value sequence and due to that, my peripheral internal configuration changed, and it stopped working as per expectations.
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A successful send sequence of 4 bytes is 0xFF,0xFF,0xFF,0xFF.
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Found wrong sequence of 4 bytes is 0x00,0xFF,0xFF,0xFF. After this sequence peripheral goes into failure.
In both failure and success cases, it is sent from the same API with a fixed register value. I also verify that the spi_transceive_dt is successful every time.
Why does this register sequence change at some random time?
Regression
- This is a regression.
Steps to reproduce
There is no specific step to reproduce it. Run for a long time, and an issue is created. But there is no specific interval.
Relevant log output
Impact
Annoyance – Minor irritation; no significant impact on usability or functionality.
Environment
I am using Zephyr "v3.5.99-ncs1-2" version.
Additional Context
No response
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