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Improve overflow check on RISCV#350

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zherczeg merged 1 commit into
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emit_cmp
Dec 9, 2025
Merged

Improve overflow check on RISCV#350
zherczeg merged 1 commit into
masterfrom
emit_cmp

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@zherczeg

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name is assigned to some of these registers, which represents their
SLJIT_TMP_R(i) index. When such register is optional, it might not be
defined on all architectures. For example, the x86-32 code generator does
not use any optional temporary registers.

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wouldn't it be clearer to say "the x86-32 code generator does not use any temporary registers at all because of the limited number of registers available"?

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It uses one temporary register. The "optional" is a second temporary register.

@zherczeg zherczeg merged commit 68f01a5 into master Dec 9, 2025
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@zherczeg zherczeg deleted the emit_cmp branch December 9, 2025 11:16
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