[fusheng-ji]

RFC #428 stack 4/4 (base test-qwennext, merge bottom-up): #466 (merged) → #467 → #468 → #469. This PR contains the earlier layers, so GitHub also shows their commits until they merge; please squash-merge this PR's own commits.

Evidence location: measurement outputs (JSON, logs) are not part of this diff. They are on the fork's pr_assets branch (links fixed to one commit). At the head: B200, H100. Older: pending/b200-qwen3-next-norm/pr469 and pending/h100-qwen3-next-norm/pr469. Commit ids in this description name the branch as rewritten on 2026-10-23; the evidence archives record the pre-rewrite ids.

What

Advances C6 of #428 (GDN recurrent response replay): two PyTorch goldens for the Qwen3-Next decode step and a GDN cache-state contract. No CUDA kernel. Claim level L0 + L1 for the goldens; L2 is not claimed.

• The recurrent golden (GatedDeltaRuleRecurrentStepOp, rl_engine/reference/linear_attn/gated_delta_rule.py) follows the arithmetic of vLLM's fused_recurrent_gated_delta_rule_packed_decode, checked line by line against fused_recurrent.py:288-335:
  • fused fp32 gating with the softplus threshold at 20;
  • no repeat_interleave (i_h = i_hv // (HV // H));
  • QK norm x / sqrt(sum(x*x) + 1e-6), scale on q after the norm;
  • a fixed 32-wide chunked sum for every contraction.
• The conv golden (CausalConv1dUpdateOp) starts the fp32 accumulator from bias and rounds each tap product to the operand dtype first, as vLLM's causal_conv1d_update does. It is here because in rollout the conv update and the recurrent step make one decode step (RFC §7.2); it can move to C4 if maintainers prefer.
• State contract. Recurrent state [num_blocks, HV, V, K] addressed by ssm_state_indices, fp32 accumulator, store rounds to the state dtype (fp32 or bf16). Conv state [num_blocks, dim, W-1] or the transposed layout (dim_first). Both goldens raise on an active index that is out of range or repeated. The two providers use different null-block rules:
  • the recurrent golden skips every index <= 0, as the provider does (fused_recurrent.py:300);
  • the conv golden skips only the null block id (0), as vLLM's causal_conv1d_update does, and raises ValueError on a negative index instead of treating it as inactive.
• Provider-agreement runner (tools/validation/models/ws1_gdn_provider_agreement.py) writes the numbers below, including the conv_silu and conv_noact_bf16 sections that locate the conv mismatches.
• Qwen3-Next provider workflow (.github/workflows/qwen3-next-provider-gpu.yml, self-hosted) runs the two check_ files, which import vLLM and are not collected by default. workflow_dispatch takes source_repository and source_sha (format-checked, as in ws1-chain-npu.yml) and checks out that commit. The job sets RL_KERNEL_REQUIRE_EXT=1, deletes any stale _C*.so and build/ before building, runs tools/checks/ci_smoke.py after the build, and fails if any provider test is skipped. Fork PRs get only a notice job.
• Other changes to existing code: test_gdn_state_contract.py is in the unit-tests list of ci.yml.

What is and is not bitwise against vLLM 0.30.0

	result
L1, golden against itself	in one batch of 64 (seed 3, all rows active), rows 0, 1, 31, 63 give bitwise the same output and state block alone, for fp32 and bf16 state. No L1 claim for the provider.
conv update, rolled state	bitwise (torch.equal), B ∈ {1, 4, 17, 64} × fp32/bf16 cache
conv update, output	not bitwise with an fp32 cache: at most 5 of 524,288 elements differ on B200 and 17 on H100 (asserted ≤ max(4, elements / 8192), i.e. 4 to 64). Cause on B200: Triton's SiLU, not the convolution; on H100 FP contraction also changes the fp32 pre-activation (Results)
recurrent step	close, not equal: fp32 state, max|d out| up to 6.10e-5 on B200 and 1.22e-4 on H100, max|d state| up to 2.98e-7 and 3.58e-7 (asserted ≤ 1e-3 / ≤ 1e-5); random inputs, one seed per batch, no real weights
composed model (L2)	not claimed. The real-checkpoint startup attempt (2026-09-30) failed before inference with VLLM batch_invariant mode is not supported for GDN_ATTN; op-level agreement says nothing about 48 composed layers

The packed kernel is the provider only in decode-only steps: a decode-only, non-speculative step takes _forward_core_decode_non_spec (qwen_gdn_linear_attn.py:1295-1307) because VLLM_ENABLE_FLA_PACKED_RECURRENT_DECODE defaults to on. VLLM_GDN_DECODE_KERNEL="cuda" is not what Qwen3-Next runs: gqa_interleaved_layout=True makes the layer fall back to "triton". Steps shared with a prefill go through causal_conv1d_fn and fused_sigmoid_gating_delta_rule_update; this golden does not target them (Scope).

Prior art & reuse decision

N/A: this PR adds PyTorch goldens and a cache-state contract, not an operator implementation, so the reuse rule does not apply. The goldens are compared against vLLM's own GDN paths (table above and Results).

Results

B200 and H100 are separate data sets; per RFC #428 §2.2 no claim is made across cards.

B200 (sm_100)

One NVIDIA B200 with no other process on it (driver 580.126.20), torch 2.13.0+cu130, vLLM 0.30.0; clean tree, extension built in place and checked to load from the checkout. Files: b200-pr469-head-e8daba53-idle-b200.

check	result at e8daba53
unit suite (five paths, Tests)	312 passed, 0 failed, 73 skipped (72 Ascend rmsnorm_ascend not compiled, 1 needs two CUDA devices)
check_qwen3_next_norm_providers.py + check_gdn_recurrent_golden.py	48 passed, 0 skipped
ws1_gdn_provider_agreement.py	rc 0; conv state bitwise equal in all 16 rows (conv output max abs diff 1.6e-2); recurrent rows within the asserted tolerances (output max abs diff 6.1e-5, state 2.0e-3), not bitwise

Earlier B200 runs (historical)

An earlier run at the same head was made locally while the GPU was shared; it gave the same results and the provider-agreement JSON is identical except for the recorded checkout path, so the idle-GPU run replaces it. Its logs: b200-pr469-head-e8daba53-b200. Earlier run at 91bf5294 (b200-pr469-b200, clean tree, idle GPU): 304 passed, 0 failed, 73 skipped; provider agreement rc 0, conv state bitwise equal in all 16 rows (conv output max abs diff 1.6e-2), recurrent rows within the asserted tolerances (output max abs diff 6.1e-5, state 2.0e-3), not bitwise. 91bf5294..e8daba53 changed Python guards, the saved-rstd reshape, the conv negative-index rejection, the workflows and comments; no kernel source.

Recurrent step vs the packed-decode provider (test_golden_matches_packed_decode_provider; B ∈ {1, 4, 17, 64}, seed=batch, bf16 I/O, use_qk_l2norm_in_kernel=True, random inputs; measured at f8d9399, before the migration; the bounds are regression bounds, not gate evidence):

state	asserted max|d out| / max|d state|	measured max|d out| over B	measured max|d state|	out elements differing (B=1/4/17/64)
fp32	≤ 1e-3 / ≤ 1e-5	1.49e-8 … 6.10e-5	≤ 2.98e-7	1 / 2 / 10 / 40
bf16	≤ 1e-3 / ≤ 5e-3	3.73e-9 … 3.05e-5	≤ 1.95e-3	2 / 2 / 14 / 36

Conv update vs causal_conv1d_update (bias=True, silu, dim_first=True, W=4, dim=8192, all rows active, one seed per batch): rolled state bitwise in all 8 cases. Output elements differing: fp32 cache 0 / 0 / 1 / 5 (max 2.44e-4 at B=17, 3.91e-3 at B=64; asserted ≤ 32 elements, max|diff| ≤ 1e-2); bf16 cache 0 / 0 / 0 / 3 (max 1.56e-2 at B=64; asserted at B ∈ {1, 17}: ≤ 32 elements, max|diff| ≤ 7e-2). The two mismatch mechanisms, both on the provider side, measured by the runner at f8d9399 on B200:

• With SiLU (Qwen3-Next's configuration): the activation. With the activation off and fp32 output the two agree bitwise. Triton lowers acc / (1 + tl.exp(-acc)) to ex2.approx and div.full.f32; applying that expression to the golden's pre-activation values reproduces the provider bitwise, and the golden equals libdevice.exp with IEEE division. About 38% of fp32 outputs differ, mostly by 1 ULP; only values straddling a bf16 rounding midpoint survive the store. No FFMA is involved, and TRITON_DEFAULT_FP_FUSION=0 changes nothing.
• No activation, bf16 output: FP contraction (fma.rn.f32x2 / FFMA) in that specialization; 1 / 0 / 4 / 14 outputs differ (max|diff| 3.9e-3), 0 with TRITON_DEFAULT_FP_FUSION=0. Qwen3-Next's decode path does not use this specialization.
• Open: the recurrent provider computes exp(g) and sigmoid(b) with Triton and the golden with PyTorch; not investigated.

Before the migration (610f1b7, one B200, extension built from a clean clone): full suite 18 failed, 3119 passed, 923 skipped against main (32b765e) 17 failed, 2942 passed, 923 skipped: no new failures, the same 2 fixed, plus 3 spawn timeouts in the multi-process TP2 tests of tests/test_vocab_parallel_logp.py that did not reproduce (alternating A/B on one node, 5 rounds each, all six cases passed every round on both sides). This PR changes no logp or tensor-parallel code. check_operator for rms_norm, rms_norm_gated and qwen3_next_rms_norm gave pass_rate=1.0000 each.

H100 (sm90)

At head e8daba53 (h100-pr469-head-e8daba53-h100): one NVIDIA H100-94GB (95830 MiB, driver 580.173.02, sm90), torch 2.13.0+cu130, vLLM 0.30.0, transformers 5.13.1, clean tree (git_dirty: false), extension loaded from the tree under test.

check	head	result
unit suite (five paths, Tests)	e8daba53	312 passed, 0 failed, 73 skipped (72 Ascend not compiled, 1 needs two CUDA devices)
check_qwen3_next_norm_providers.py + check_gdn_recurrent_golden.py	e8daba53	48 passed, 0 skipped
ws1_gdn_provider_agreement.py	e8daba53	rc 0; conv state bitwise equal in all 16 rows (conv output max abs diff 1.5625e-2); recurrent rows within the asserted tolerances (output max abs diff 1.2207e-4, state 1.9531e-3), not bitwise

Provider agreement on H100 (same runner and head; the B200 numbers above are not carried over): recurrent step, fp32 state: max|d out| up to 1.22e-4, max|d state| up to 3.58e-7, out elements differing 0 / 1 / 11 / 42 (B=1/4/17/64); bf16 state: max|d out| up to 6.10e-5, max|d state| up to 1.95e-3, 0 / 3 / 15 / 43. Conv update: rolled state bitwise in all 16 rows; output elements differing with an fp32 cache 1 / 0 / 3 / 17 (max 3.91e-3 at B=64), with a bf16 cache 0 / 0 / 0 / 4 (max 1.56e-2 at B=64). The B200 mechanism does not carry over to H100 unchanged: with Triton's default FP contraction the runner's preactivation_mismatch_elements (golden vs provider before the activation) is 2,328 / 9,468 / 39,955 / 150,108 elements for B=1/4/17/64, against 0 on B200, and it is 0 on H100 with contraction disabled; the SiLU stage then differs in 51 to 52% of outputs (37 to 38% on B200). With the activation off and a bf16 output, 1 / 0 / 4 / 16 outputs differ with contraction on and 0 with it off. All of these stay inside the asserted bounds (unit suite and provider checks pass).

Earlier snapshot (h100-pr469-h100): unit suite 304 passed, 0 failed, 73 skipped at 836c483d; provider agreement rc 0 at d1129d9f (now 91bf5294, same tree).

Status

• Head 2b64780b, on top of [WS1][CUDA][Qwen3-Next] Gated RMSNorm CUDA kernel for the GDN block (RFC #428 stack 3/4) #468 (merged into test-qwennext). CI is green on this head: lint, unit-tests, docs, DCO and the bot review pass. provider and ws1-gtest skip because no self-hosted runner is attached.
• Every automated-review finding was answered in its own thread: fixed (gated-op guard, rstd reshape, workflow pinning and fail-closed checks, conv negative indices) or declined with the code or a measurement. The two threads on the self-hosted trust model (same-repository PRs run on the runner; source_repository is only format-checked) follow ws1-chain-npu.yml and await the maintainers' preference.
• Not in this PR: speculative decode / MTP, backward (RFC [RFC][Qwen3-Next-80B-A3B-Instruct][CUDA/ROCm] VIME/vLLM operator-level train-rollout consistency roadmap, ablation matrix, and integration plan #428 C7, supports_backward=false), a registry entry, the paged allocator, TP sharding, ROCm/Ascend.

History

• 2026-10-28 (review): @inaniloquentee's review found that the conv reference's SiLU backward returns NaN for pre-activations below -88.7 (exp(-acc) overflows); e3e04844 computes that stage in an autograd.Function whose forward is unchanged and whose backward is overflow-free, with a regression test. The OpenCodeReview round that followed is answered in its own threads and comments: 70591e9d makes the fp32-widening and use_qk_l2norm tests independent of the code they check and documents the conv skip rule, 433c6d33 makes the bias-before-taps test discriminate (the old values rounded the same in either order) and hardens two lines of ws1_gdn_provider_agreement.py, and ef58b271 makes the state-index skip rule an explicit argument of _validate_state_indices (the conv op no longer borrows the recurrent rule), narrows a comment on the chunked sum, and adds a sign_differs count to the agreement tool's ULP histogram. The H100 and B200 runs above were not repeated; these commits change a test, a docstring, the backward of the SiLU stage and the agreement tool, not forward values. 2b64780b passes the fork-PR notice's fields through env:, makes the agreement tool keep its fusion-on measurements when the fusion-off child fails and exit 1 when that arm did not hold, and scales the conv-output element budget with the tensor (max(4, numel / 8192), 4 to 64 elements for batches 1 to 64).
• 2026-10-26 (review): two OpenCodeReview rounds on the stack (the bot re-reviews every PR's whole diff after each push); every finding of these two rounds is answered in its own thread or comment, most as repeats of earlier answers or as not applicable with the code reference. Fixes in this PR: ba3e366c triggers the provider job on rl_engine/config/** and drops a redundant path entry. The fixes of the PRs below it are merged in; new head 3b75d308. Kernel arithmetic is unchanged, so the measured results stand.
• 2026-10-26 (later): merged test-qwennext after [WS1][CUDA][Qwen3-Next] C1: zero-centred RMSNorm references and CUDA kernel (RFC #428 stack 2/4) #467 landed (c382dd4b), through [WS1][CUDA][Qwen3-Next] Gated RMSNorm CUDA kernel for the GDN block (RFC #428 stack 3/4) #468's head acf4aa56, in 27212b65. The conflicts were between this PR's 2026-10-25 bot-review fixes and [WS1][CUDA][Qwen3-Next] Gated RMSNorm CUDA kernel for the GDN block (RFC #428 stack 3/4) #468's later versions of the same changes (workload scope check and its test, plot docstring); [WS1][CUDA][Qwen3-Next] Gated RMSNorm CUDA kernel for the GDN block (RFC #428 stack 3/4) #468's versions were taken, and ci.yml keeps this PR's test_gdn_state_contract.py. The diff against [WS1][CUDA][Qwen3-Next] Gated RMSNorm CUDA kernel for the GDN block (RFC #428 stack 3/4) #468 is again only the C6 files.
• 2026-10-26: B200 re-run at the head e8daba53 on an idle GPU, replacing the run made while the GPU was shared (same results); Results restructured with the older B200 runs collapsed; evidence links retargeted to the current pr_assets commit.
• 2026-10-25: bot-review fixes (82114efb gated-op API-version guard in place of an assert; 2d4b4d2a rstd reshape; 8c4746eb manifest KeyError → WorkloadError; 0e0fbd77 conv rejects negative indices; 55cca5e6 workflow dispatch pinning, RL_KERNEL_REQUIRE_EXT, ci_smoke, stale-_C removal; e8daba53 fail on any skipped provider test; abc35461, 72d03f28, 41299728 comments).
• 2026-10-25: DCO. d1129d9f (the runner import-path fix) lacked a sign-off, and a remediation commit is not accepted here; it was re-created with the trailer as 91bf5294 (identical tree).
• 2026-10-23: history rewritten (evidence directories removed from every commit, sign-offs added); ids in this description name the rewritten commits.
• Repository refactor: merged upstream test-qwennext (a5a92ecf) as requested in RFC [RFC][Qwen3-Next-80B-A3B-Instruct][CUDA/ROCm] VIME/vLLM operator-level train-rollout consistency roadmap, ablation matrix, and integration plan #428; code moved to rl_engine/reference/linear_attn, tests/models/qwen3_next, tools/validation/models. The old tests/test_*.py and scripts/... commands no longer apply. After migration: 298 passed, 73 skipped.
• 2026-10-08: merged the aligned [WS1][CUDA][Qwen3-Next] Gated RMSNorm CUDA kernel for the GDN block (RFC #428 stack 3/4) #468 (0194066): 283 passed (72 skipped, all Ascend) across the GDN state contract and norm suites, 40 golden/provider checks passed, and the four Qwen3-Next C3/C4 gates passed. Added L1 for the conv golden (6d3d665, test_conv_golden_is_batch_invariant): every sequence of a batch of 257 alone plus sub-batches of 2, 7 and 64 at other offsets and a shuffled order, contiguous and shuffled cache blocks, fp32 and bf16 caches, with and without bias and SiLU, three seeds; output rows and rolled state blocks bitwise unchanged in all 8 configurations, and a deliberately batch-dependent golden fails it.
• 2026-10-04: re-stacked linearly onto [WS1][CUDA][Qwen3-Next] Gated RMSNorm CUDA kernel for the GDN block (RFC #428 stack 3/4) #468 with every commit signed off (DCO); 0b41350 makes _chunked_sum pad a last dimension that is not a multiple of 32 instead of falling back to an unordered .sum (CodeRabbit finding; Qwen3-Next has K=V=128, so no number changed).
• Retracted: the earlier 1024-step and prefill-vs-decode tables (dbb8d00, no checked-in runner); the first fusion-off reading of the runner (5216a6c, the in-process knob reused the fused kernel; fixed in 10e5230).

Tests

At head e8daba53, extension built in place. B200 and H100 below are separate measurements at this head:

pytest tests/models/qwen3_next tests/ops/norm/test_rms_norm.py tests/ops/autograd/test_vjp_fp32.py tests/runtime/test_dispatch.py tests/validation/operators/test_ws1_gtest_gpu.py -q -p no:randomly -rfs
pytest -q -rs tests/models/qwen3_next/check_qwen3_next_norm_providers.py tests/models/qwen3_next/check_gdn_recurrent_golden.py   # needs CUDA + vLLM 0.30.0
python tools/validation/models/ws1_gdn_provider_agreement.py > gdn_provider_agreement.json   # output outside the tree

command	B200 e8daba53	H100 e8daba53
unit suite	312 passed / 0 failed / 73 skipped	312 passed / 0 failed / 73 skipped
provider checks	48 passed / 0 skipped	48 passed / 0 skipped
provider-agreement runner	rc 0	rc 0

Skips, all environment: 72 × rmsnorm_ascend kernel not compiled (needs KERNEL_ALIGN_FORCE_ASCEND=1 on an Ascend host), 1 × needs at least two CUDA devices. The check_ files import vLLM and test_framework_operator_integrations.py asserts "vllm" not in sys.modules, so they run only when named. check_operator cannot run the C6 goldens (no gtest spec, no registry entry); the norm regressions from the lower PRs are listed in #468.

Scope / Known limitations

• Provider coverage. The recurrent golden matches rollout only in decode-only steps. A kernel-level replay (pr469/mixed-step on pr_assets; library kernels with synthetic inputs, no layer, scheduler or checkpoint; one idle B200, vLLM 0.30.0) shows that a decode row's recurrent state differs between a decode-only step, which uses the packed kernel, and a mixed step, where the layer peels the decodes off and uses fused_sigmoid_gating_delta_rule_update. The mixed-step result is bitwise identical for a 64-token and a 1031-token prefill and to a decode-only step with the packed path off, so the difference comes from the kernel choice, which depends on whether a prefill shares the step, and not from the prefill's tokens. The size of the difference depends on the fixture. Over 200 random single-row fixtures with fp32 state, the number of differing state elements of the row is 22,181 to 164,510 of 524,288 at TP1 shapes (median 83,588) and 59 to 55,226 of 131,072 at TP4 per-rank shapes; with bf16 state it is 0 to 18 and 0 to 7. One bf16 output element differs in 34 of 200 fixtures at TP1 shapes with fp32 state (two elements in 4) and in 11 of 200 at TP4 per-rank shapes (never more than one); with bf16 state, 39 and 15 fixtures. An earlier single-fixture figure of 75,146 differing state elements lies inside the TP1 range; it was not reproduced exactly. The upstream change [Model] Enable batch-invariant mixed decode and prefill for Qwen GDN vllm-project/vllm#49827, which routed cached decode rows through the packed kernel in mixed steps as well, was closed on 2026-10-13 and superseded by the open, still work-in-progress [WIP][Model] Share recurrent arithmetic for Qwen GDN batch invariance vllm-project/vllm#60033, which uses the existing recurrent kernel for non-speculative tokens under VLLM_BATCH_INVARIANT=1 (I have not run it against this golden); disabling VLLM_ENABLE_FLA_PACKED_RECURRENT_DECODE is the other route, and then the golden's target would have to change.
• Not a transcription. Softplus is torch.log1p(torch.exp(safe)) against the kernel's tl.log(1.0 + tl.exp(x)); exp/log become fast ops when FLA_USE_FAST_OPS=1 (the goldens model the default); the 32-wide chunked sum fixes the reduction shape per row (the argument for L1) but is not the kernel's tree reduction, which is why the golden is not bitwise against it.
• Production uses no conv bias (conv1d is built with bias=False); the only bias-free provider comparison is one hand-built cancellation input. dim_first=False is compared only golden against golden.
• vLLM does not check index values in causal_conv1d_update even with validate_data=True; an out-of-range index there is an unchecked memory access (read from the source, not exercised).
• bf16 recurrent state is a differential experiment (the strict profile uses fp32): one fixed fixture (B=8, 128 steps, seed 11), a regression bound, not evidence of a general plateau or of any bound on model logits.
• Prefill side. An fp32 q/k/v prefill is unavailable on both default backends (the FLA chunked kernel rejects fp32 q/k/v; FlashInfer's SM100 prefill paths do too, read from flashinfer 0.6.18.post1, not run). The opt-in CuteDSL backend was not checked.
• MTP. Speculative decode is out of the first claim (RFC §2.2); in steps with draft tokens the target model's GDN path changes.
• Left as is, no behaviour change: no docs/operators/ page (the design note docs/archive/design/rfc428-c6-gdn-recurrent-replay.md is the only documentation); the runner calls the check_ file's private helpers; _chunked_sum re-implements the chunking of shape_invariant_rstd; some function-local imports; history in a few docstrings.
• Hardware. sm_100 and sm_90 only, no claim across cards.

Summary by CodeRabbit

• New Features

  • Added Qwen3-Next zero-centred and gated RMSNorm operators, with PyTorch and CUDA implementations and support for SiLU or sigmoid gating.
  • Added PyTorch reference operations for Gated DeltaNet recurrent steps and causal convolution updates.
  • Added operator guides, workload validation, and performance and accuracy reports for Qwen3-Next normalization.

• Bug Fixes

  • Improved RMSNorm input validation and CUDA dispatch fallback when required GPU support is unavailable.
  • Preserved inactive cache entries and returned zero outputs for inactive or empty batches.

• Tests

  • Expanded CPU and GPU checks for normalization, recurrent-state behavior, provider agreement, and batch invariance.

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• docs/operators/qwen3-next-rms-norm.md
• docs/usage/evidence/qwen3-next-rms-norm-b200/report.json
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• rl_engine/_C.pyi
• rl_engine/kernels/ops/cuda/norm/rmsnorm.py
• rl_engine/kernels/ops/pytorch/linear_attn/gated_delta_rule.py
• rl_engine/kernels/registry.py
• scripts/plot_qwen3_next_norm_evidence.py
• scripts/qwen3_next_norm_evidence.py
• tests/check_gdn_recurrent_golden.py
• tests/test_gdn_state_contract.py
• tests/test_qwen3_next_norm.py
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Walkthrough

📝 Walkthrough

Walkthrough

This change adds Qwen3-Next zero-centred and gated RMSNorm operators for PyTorch and CUDA. It adds workload validation, dispatch support, tests, CI checks, and operator documentation. It also adds PyTorch references for GDN recurrent and convolution steps, with provider checks and replay documentation.

Changes

Qwen3-Next normalization

Layer / File(s)	Summary
CUDA kernels and bindings csrc/cuda/rmsnorm.cu, csrc/ops.cpp, rl_engine/_C.pyi	RMSNorm forward and input-gradient APIs accept a weight offset. The CUDA implementation adds gated RMSNorm operations, validation, and launch checks. The bindings declare API version 2.
Python operators and dispatch rl_engine/kernels/ops/cuda/norm/rmsnorm.py, rl_engine/kernels/ops/pytorch/norm/*, rl_engine/kernels/registry.py, rl_engine/tests/test_dispatch.py, rl_engine/tests/test_rms_norm.py	Python operators add zero-centred and gated RMSNorm variants. Dispatch tests cover CUDA priority, PyTorch fallback, and extension API compatibility.
Norm workload and invariance harness rl_engine/kernels/gtest/*, rl_engine/testing/qwen3_next_*, rl_engine/testing/ws1_workload.py, scripts/check_*_invariance.py, tests/test_qwen3_next_workload.py, tests/test_ws1_ascend_closeout.py, tests/test_ws1_gtest_gpu.py, ci/run_ws1_gtest.sh	The Qwen3-Next manifest defines norm operators, dimensions, fixtures, and backend profiles. Model-scoped adapters and invariance scripts use the manifest; tests cover validation and adapter selection.
Verification and operator documentation tests/test_qwen3_next_norm.py, tests/check_qwen3_next_norm_providers.py, .github/workflows/ci.yml, .github/workflows/qwen3-next-provider-gpu.yml, .github/workflows/ws1-gtest-gpu.yml, docs/operators/*, docs/.nav.yml, docs/usage/evidence/*, scripts/qwen3_next_norm_evidence.py, scripts/plot_qwen3_next_norm_evidence.py	Tests cover RMSNorm arithmetic, gradients, invariance, and provider comparisons. CI workflows run selected checks. Operator documentation, evidence reports, and scripts record and plot measurements.

GDN reference operations and provider analysis

Layer / File(s)	Summary
Paged-state reference operators and contracts rl_engine/kernels/ops/pytorch/linear_attn/*, tests/test_gdn_state_contract.py	PyTorch reference operators implement recurrent and causal-convolution steps over paged state. Tests cover index validation, inactive rows, state preservation, and arithmetic behavior.
Golden checks and provider measurements tests/check_gdn_recurrent_golden.py, scripts/ws1_gdn_provider_agreement.py	Golden checks compare recurrent and convolution outputs and state with providers. The measurement runner reports batch comparisons, kernel details, and fusion-off results.
Provider replay design and workflow docs/design/rfc428-c6-gdn-recurrent-replay.md, .github/workflows/qwen3-next-provider-gpu.yml	The RFC documents provider paths, arithmetic and state contracts, measurements, and replay boundaries. The GPU workflow runs targeted provider checks.

Priority: Normal

Estimated code review effort: 5 (Critical) | ~120 minutes

Change: Feature

Merge Risk: Minimal · previous review c2140

The previously identified reduction issue is fixed at the reviewed head. No actionable issue remains before normal merge checks.

Security Architecture Review

Security architecture risk: 🔵 Low · up to c2140

The inspected paths retain input validation and avoid mutating caller-owned reference state. No new privilege or isolation bypass was demonstrated, but compatibility across mixed builds and production state recovery remain only partially established.

Retained concerns
No architecture-level concerns identified.

Security review details

Security Blast Radius

• inferred — The inspected native entrypoints require an in-process caller supplying CUDA tensors. Their execution scope is the loaded extension process and the input tensor's device and current stream. The examined path does not establish remote, cross-tenant, or privileged-service reachability.

Trust Boundaries and Controls

• observed — Public normalization bindings validate CUDA residency, contiguity, supported dtypes, dimensions, and device agreement before internal launches. Gated inputs must match the input shape and dtype, activation selectors are restricted, and backward inputs receive consistency checks. These native controls remain applicable even when Python assertions are disabled.

Resilience and Maintainability Implications

• inferred — Out-of-place updates contain per-call computation failures by leaving input state unchanged. They do not enforce cross-call block ownership, serialize concurrent updates, or atomically publish recurrent and convolution results together. Production interruption, retry, rollback, and recovery guarantees remain outside the evidenced reference integration.

Hardening Proposals

• proposed — Consider applying explicit API-version compatibility checks to gated construction and dispatch as well as symbol checks, preventing future mixed-build control drift. No incompatible gated build was demonstrated in this review.
• proposed — Before adding a production provider bridge, define provider-specific sentinel validation, request-to-block authority, serialized state publication, and interruption recovery. Do not treat successful reference execution as validation of raw-provider metadata or combined state commits.

Pre-merge checks: 3 · 1

Failed checks: 1 warning

Check name	Status	Explanation	Resolution
Linked Issues check		Issue #49827 requires coding changes for three boundaries: packed recurrent decode for cached rows in mixed decode/prefill steps, fixed FlashInfer prefill selection under batch-invariant mode, and 64-…	Implement the Qwen-specific batch-invariant path from #49827. Route cached rows through packed recurrent decode in mixed steps. Select the fixed FlashInfer prefill implementation under batch-invariant mode. Align non-final chunked-prefill c…

Passed checks: 3 passed

Check name	Status	Explanation
Out of Scope Changes check		The PR-owned changes remain related to GDN decode-step validation: PyTorch recurrent and convolution goldens, cache-state contract tests, provider comparison checks, CI wiring, and the C6 design note.…
Title check		The title clearly identifies the main change: Qwen3-Next GDN decode-step goldens and recurrent/convolution state-contract work. It is specific, concise, and includes the relevant RFC and stack context…
Description Check		Check skipped - CodeRabbit’s high-level summary is enabled.

Full details: Out of Scope Changes check

Explanation

The PR-owned changes remain related to GDN decode-step validation: PyTorch recurrent and convolution goldens, cache-state contract tests, provider comparison checks, CI wiring, and the C6 design note. They support investigation and validation of the linked Qwen GDN behavior. The RMSNorm implementation and related files are identified as lower stacked PR changes, not as new scope for this PR.

Full details: Title check

Explanation

The title clearly identifies the main change: Qwen3-Next GDN decode-step goldens and recurrent/convolution state-contract work. It is specific, concise, and includes the relevant RFC and stack context.

Full details: Linked Issues check

Explanation

Issue #49827 requires coding changes for three boundaries: packed recurrent decode for cached rows in mixed decode/prefill steps, fixed FlashInfer prefill selection under batch-invariant mode, and 64-token scheduler chunk alignment. This PR adds PyTorch GDN goldens, decode-only provider checks, state-contract tests, and documentation. The current description explicitly excludes mixed-step routing, prefill, and scheduler changes. The required #49827 implementation and its mixed-step, prefill, chunk-boundary, and online regressions are not present.

Resolution

Implement the Qwen-specific batch-invariant path from #49827. Route cached rows through packed recurrent decode in mixed steps. Select the fixed FlashInfer prefill implementation under batch-invariant mode. Align non-final chunked-prefill calls to the 64-token grid. Add the required boundary and online regressions.

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• 🪄 Fix CodeRabbit comments on this PR

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Inline comments:
Review comments at
@rl_engine/kernels/ops/pytorch/linear_attn/gated_delta_rule.py:
- Around line 76-90: Update _chunked_sum so non-multiple-of-32 widths use the
same fixed chunk-order reduction instead of falling back to a whole-axis sum;
pad the tail to the next _REDUCTION_CHUNK boundary before reshaping and
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📥 Commits

Reviewing files that changed from the base of the PR and between 11cac8c and 62b481b.

📒 Files selected for processing (36)

• .github/workflows/ci.yml
• .github/workflows/qwen3-next-provider-gpu.yml
• ci/run_ws1_gtest.sh
• csrc/cuda/rmsnorm.cu
• csrc/ops.cpp
• docs/.nav.yml
• docs/design/rfc428-c6-gdn-recurrent-replay.md
• docs/operators/README.md
• docs/operators/qwen3-next-rms-norm-gated.md
• docs/operators/qwen3-next-rms-norm.md
• rl_engine/_C.pyi
• rl_engine/kernels/gtest/gradient_adapters.py
• rl_engine/kernels/gtest/operator_inputs.py
• rl_engine/kernels/gtest/operator_specs.py
• rl_engine/kernels/ops/cuda/norm/rmsnorm.py
• rl_engine/kernels/ops/pytorch/linear_attn/__init__.py
• rl_engine/kernels/ops/pytorch/linear_attn/causal_conv1d.py
• rl_engine/kernels/ops/pytorch/linear_attn/gated_delta_rule.py
• rl_engine/kernels/ops/pytorch/norm/qwen3_next_rms_norm.py
• rl_engine/kernels/ops/pytorch/norm/rms_norm.py
• rl_engine/kernels/registry.py
• rl_engine/testing/qwen3_next_norm_manifest.json
• rl_engine/testing/qwen3_next_workload.py
• rl_engine/testing/ws1_workload.py
• rl_engine/tests/test_dispatch.py
• scripts/check_forward_invariance.py
• scripts/check_gradient_invariance.py
• scripts/ws1_gdn_provider_agreement.py
• tests/check_gdn_recurrent_golden.py
• tests/check_qwen3_next_norm_providers.py
• tests/test_gdn_state_contract.py
• tests/test_qwen3_next_norm.py
• tests/test_qwen3_next_workload.py
• tests/test_rms_norm.py
• tests/test_ws1_ascend_closeout.py
• tests/test_ws1_gtest_gpu.py

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[fusheng-ji]

OpenCodeReview · tests/models/qwen3_next/test_gdn_state_contract.py (L55): This case passes -1 to the GDN op and expects it to be treated as inactive (cache untouched, zero output), while test_conv_rejects_negative_state_indices right below asserts the conv op rejects -1.

The two ops have different index contracts on purpose; stated in a comment in 70591e9d, no behaviour change. The GDN provider skips every index <= 0 (state_idx <= 0), so -1 is a skipped row there, as NULL_BLOCK_ID in gated_delta_rule.py documents. vLLM's conv provider skips only == 0, so a negative conv index is a real index and the reference rejects it, which the next test pins. The comment above the ("gdn", torch.tensor([0, -1, 0])) case now says this.

[fusheng-ji]

OpenCodeReview · tests/models/qwen3_next/test_gdn_state_contract.py (L81-L82): This test does not actually distinguish bias-before-taps from bias-added-last, so it cannot catch the regression its comment claims to pin.

Confirmed and fixed in 433c6d33. In both old cases the partial sums round to the same value in either order. I moved the bias after the taps in the op and the old test still passed. The test now uses two products of 3.0 and a bias of 1e8 (fp32 spacing 8 there): bias first gives 1e8 (each 1e8 + 3 rounds back), bias last gives 100000008. It asserts 1e8 and that this differs from (3.0 + 3.0) + 1e8. With the bias moved after the taps, the new test fails.

[fusheng-ji]

OpenCodeReview · tools/validation/models/ws1_gdn_provider_agreement.py (L402-L411): _detect_compiled_conv_variants creates a TemporaryDirectory named triton-nofusion-* ... its output is parsed with json.loads(child.stdout) ... any deprecation banner ... printed on stdout will make json.loads raise.

Fixed in 433c6d33: the report is now read from the child's last stdout line, so a banner printed before it cannot break the parse. The child's stderr is not captured: it goes to the parent's stderr, so a CUDA initialisation error in the child is visible there, and check=True raises with the exit status. The function in question is _conv_report_without_fusion; the temporary directory is the child's Triton cache and is removed when the run ends. I ran the tool on a GPU after the change: it exited 0 and the report contains the fusion-on and fusion-off variant lists.

[fusheng-ji]

OpenCodeReview · tools/validation/models/ws1_gdn_provider_agreement.py (L298): inp here is built with check._conv_inputs(batch, torch.float32, seed=batch), whose x is bf16. The "fp32-output twin" is therefore not a twin of the same computation ...

Not changed. The fp32 arm already is what the finding suggests: line 298 runs check._run_conv_pair(dict(inp, x=inp["x"].float()), activation=None). x.float() of a bf16 tensor is exact, so both arms use the same values and differ only in the output dtype. b_ref and d_ref are both the provider's output (the first element of _run_conv_pair), not the golden's, so provider_eq_rne_of_fp32_out compares the provider's bf16 output with the provider's fp32 output rounded to bf16, which is the dtype specialization it is named for. The golden's output is used only for the mismatch counts.

[fusheng-ji]

OpenCodeReview · tools/validation/models/ws1_gdn_provider_agreement.py (L281): differ = torch.nonzero(b_ref.view(torch.int16) != b_got.view(torch.int16)) hard-codes a 16-bit view while the sibling branch uses _bit_mismatches ...

Partly changed in 433c6d33. Both tensors are bf16 here by construction: x is bf16 and the golden returns x.dtype, so the 16-bit view is correct. I did not reuse _bit_mismatches, which asserts equal dtypes and would stop the run in the same way. Instead the line before the view now asserts b_ref.dtype == b_got.dtype == torch.bfloat16 with both dtypes in the message, so a dtype change is reported by name and not as a RuntimeError from view.

[fusheng-ji]

OpenCodeReview · .github/workflows/qwen3-next-provider-gpu.yml (L124-L128): The fail-closed log parsing is fragile: -rs short-summary skip lines are prefixed with the module path (SKIPPED [1] tests/...), so the anchored ^SKIPPED alternative never matches, and [0-9]+ skipped does not match pytest's 1 skipped in 3.2s summary line.

Not changed; both statements are wrong for the -rs format. Each -rs line starts with SKIPPED and the path follows it, so ^SKIPPED matches. [0-9]+ skipped matches the 1 skipped inside 1 skipped in 3.2s. I ran the step's patterns on sample logs: SKIPPED [1] tests/models/qwen3_next/check_gdn_recurrent_golden.py:30: ... with 1 passed, 1 skipped in 3.2s is caught, 1 skipped in 3.2s alone is caught, 5 passed in 2.0s is not. A run that skips one module and passes another is therefore caught. See also r4372859876 .

[fusheng-ji]

OpenCodeReview · rl_engine/reference/linear_attn/gated_delta_rule.py (L61-L62): _validate_state_indices hardcodes the recurrent provider's rule indices > NULL_BLOCK_ID ... but it is also used by CausalConv1dUpdateOp._update, whose contract is different.

Fixed in ef58b271, as suggested. _validate_state_indices takes skip_negative (default True, the recurrent rule: every index <= 0 is skipped). With False it skips only NULL_BLOCK_ID, so a negative index is an active row and fails the range check. The conv op passes False. test_state_index_helper_skip_rule_is_explicit pins both modes.

[fusheng-ji]

OpenCodeReview · rl_engine/reference/linear_attn/causal_conv1d.py (L164-L168): The conv provider's skip rule (== NULL_BLOCK_ID only) is enforced by a check that runs after _validate_state_indices ...

Fixed in ef58b271, together with the finding on gated_delta_rule.py L61-L62. The conv op now rejects a negative index first, before any other index check, and then validates the rest with skip_negative=False, so the activity mask no longer depends on the recurrent rule. test_conv_rejects_negative_state_indices still passes with the same message.

[fusheng-ji]

OpenCodeReview · rl_engine/reference/linear_attn/gated_delta_rule.py (L90): The docstring and shape_invariant_rstd ... only keep the fixed-order reduction when the reduced width is a multiple of _REDUCTION_CHUNK ... The batch-invariance argument this file relies on (L1) therefore holds only when k_dim/v_dim are multiples of 32.

The claim was broader than the code, so the comment is narrowed in ef58b271; the code is unchanged. Padding with exact zeros fixes the chunk boundaries for every width, but the order inside a 32-wide chunk is that of sum over a length-32 axis. The comment now says that, and that batch invariance of the whole contraction is checked bitwise at K = V = 128 (test_golden_is_batch_invariant). The L1 claim of this PR is for Qwen3-Next's dimensions, which are multiples of 32. I did not reject other widths; the op accepts them and does not claim invariance for them.

[fusheng-ji]

OpenCodeReview · .github/workflows/qwen3-next-provider-gpu.yml (L119-L128): Skip detection relies on grepping human-readable pytest output ... Any pytest config/plugin ... that changes the summary wording would make the guard silently pass despite skipped provider checks.

Not changed; it fails closed instead. Besides the skip scan, the step ends with grep -Eq '[0-9]+ passed': if a plugin changed the summary wording so that skips were no longer recognised, the passed count would not be recognised either, and the step would fail. The step passes the options itself (-q -rs), pytest exits non-zero for a failed or errored run, and the two modules contain no xfail. I checked the patterns on sample logs in the earlier reply on this: issuecomment-6467296909. Counting from --junitxml would add a second parser for the same information; I did not add one.

[fusheng-ji]

OpenCodeReview · .github/workflows/qwen3-next-provider-gpu.yml (L97): The concurrency group is qwen3-next-provider-gpu-${{ github.ref }}, so two runs on different refs can execute simultaneously on the same self-hosted runner (and this deletes _C*.so / build across the whole checkout).

Not changed. A self-hosted runner executes one job at a time, so two runs from different refs queue for a free runner and do not run on the same one together. Each runner registered for the label has its own work directory, so the cleanup in this job (find . -name '_C*.so', rm -rf build) only touches the checkout of the runner that runs it. The group is scoped by ref so that a newer push to the same branch does not run alongside an older one (cancel-in-progress: false keeps the older run). The cleanup is there because the runner is long-lived and a stale _C from an earlier run of the same checkout would otherwise let setuptools skip the rebuild.

[fusheng-ji]

OpenCodeReview · .github/workflows/qwen3-next-provider-gpu.yml (L89-L90): Exact string equality on torch.__version__/vllm.__version__ fails on legitimate installs whose local version tag differs ...

Not changed; the exact match is the point. The step is named "Require the audited runtime", and the runner is registered for CUDA 13 with torch 2.13.0+cu130 and vLLM 0.30.0, the runtime of the H100 and B200 evidence in this PR. A different local tag (+cu128) or a .post1 build is a different build that the provider comparison has not been run against, so the job should stop there. A prefix match would run it on such builds and still report the pinned numbers.

[fusheng-ji]

OpenCodeReview · tools/validation/models/ws1_gdn_provider_agreement.py (L405-L413): The fusion-off child's report is parsed from stdout.strip().splitlines()[-1]. Any library banner/traceback printed to stdout after the JSON line makes this raise ... and check=True means a child crash surfaces as an uncaught CalledProcessError instead of a reported result.

Not changed; this follows the fix in issuecomment-6467295876. The fusion-off child is a measurement, not an introspection of Triton internals: if it crashes, the run should fail with the child's exit status and its stderr (which goes to the parent's stderr) and not produce a report that silently lacks the arm. An "unavailable" payload would also make fusion_check and the fusion comparison say less than the run was asked to measure. The child writes the report with its last print, so nothing of this program follows the JSON line.

[fusheng-ji]

OpenCodeReview · tools/validation/models/ws1_gdn_provider_agreement.py (L244): _ulp_histogram and _bf16_ulps compute "ULP distance" by integer-subtracting raw bit patterns. Across zero this is not a ULP count.

Partly right; changed in ef58b271. _bf16_ulps does not subtract bit patterns: it divides the absolute difference by one bf16 ULP at the magnitude of the reference. _ulp_histogram does, so its >4 bucket also holds elements whose signs differ. The histogram now has a sign_differs count, and the docstring says that >4 minus sign_differs is the number of same-sign elements more than 4 ULP apart; the other values are unchanged. In a local run of the tool at this head on a B200 (batches 1, 4, 17 and 64), sign_differs is 0 in all four, so the >4 counts there (10, 25, 106 and 412) are all same-sign. The reports already on pr_assets were made before this key existed.

[fusheng-ji]

OpenCodeReview · .github/workflows/ci.yml: This suits the CPU run only if the file is importable without CUDA: it imports CausalConv1dUpdateOp and GatedDeltaRuleRecurrentStepOp at module scope ...

Not changed. The finding itself says collection is safe today. test_gdn_state_contract.py has no check_-style CUDA skipif on purpose: its docstring says it holds the provider-independent cache contracts collected in the ordinary CPU suite, and it runs on CPU tensors only. The unit-tests job runs it with no GPU, and I ran it with CUDA_VISIBLE_DEVICES empty (116 passed with the other Qwen3-Next test files). A CUDA-only import added to the reference modules would fail this job at once, which is the signal wanted.

[fusheng-ji]

OpenCodeReview · .github/workflows/qwen3-next-provider-gpu.yml (L59-L60): ${{ github.event.pull_request.head.repo.full_name }} and head.sha are attacker-controlled strings being interpolated directly into a run: shell script.

Fixed in 2b64780b, as suggested: both values now go through env: (HEAD_REPO, HEAD_SHA) and are printed with printf '%s'. In practice GitHub restricts repository names to letters, digits, ., - and _, and the sha is hex, but nothing in the script should depend on that.

[fusheng-ji]

OpenCodeReview · .github/workflows/qwen3-next-provider-gpu.yml (L121): ... the pull_request trigger means the whole tests/models/qwen3_next/** tree ... executes on the self-hosted runner for any same-repo PR ... restrict the trigger to a trusted branch push/workflow_dispatch.

Not changed; same answer as r4372884187, r4387544050 and r4399770043. A pull request from a fork never reaches the self-hosted runner. A same-repository pull request needs write access to the repository, and the trust model is the one ws1-chain-npu.yml already uses here. It is open for the maintainers to say they prefer workflow_dispatch only.

[fusheng-ji]

OpenCodeReview · tools/validation/models/ws1_gdn_provider_agreement.py (L497-L500): fusion_off_effective is only written into the report; main still returns 0 when it is false ...

Fixed in 2b64780b. After printing the report, main exits 1 with a message when fusion_check.fusion_off_effective is false, which includes the case where the variants could not be listed (an empty list is not effective), and when the fusion-off child failed (fusion_off_error). With --skip-fusion-off there is no such check. On a B200 run at this head with batches 1 and 4 the tool exits 0 and fusion_off_effective is true.