Set SPI clock line idle polarity for CPOL=1

[kbsriram]

Fixes #9074

Manually verified with this code before and after the change.

import board
import bitbangio
import digitalio
import time


def doit():
    with digitalio.DigitalInOut(board.GP13) as en:
        en.switch_to_output(value=True)
        time.sleep(1)
        with bitbangio.SPI(clock=board.GP15, MOSI=board.GP14) as spi:
            spi.try_lock()
            spi.configure(baudrate=10, polarity=1, phase=0, bits=8)
            en.switch_to_output(value=False)
            spi.write(b"\xaa")
            en.switch_to_output(value=True)

Before

After

[tannewt]

Thank you!