cpu_ibex: Fix wishbone address semantics#5
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DawidPietrykowski merged 1 commit intoantmicro:masterfrom Feb 6, 2025
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While IBEX supplies addresses as they are, the [Wishbone spec][1] mandates that ADR_O be addressed in units of data port size, the lower bits being determined by SEL_O. A similar misrepresentation is present in Renode cosimulation integration, these fixes need to go in tandem. [1]: https://wishbone-interconnect.readthedocs.io/en/latest/02_interface.html#master-signals
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While IBEX supplies addresses as they are, the Wishbone spec mandates that ADR_O be addressed in units of data port size, the lower bits being determined by SEL_O. A similar misrepresentation is present in Renode cosimulation integration, these fixes need to go in tandem.
Upstream PR: renode/renode#727
The upstream change is intended to be used by CoreBlocks Open Source RISC-V CPU for integration with Renode. Currently it would need to be worked around by using extra conversion, like the suggested one here, but inverted.
Context: kuznia-rdzeni/coreblocks#778