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cpu_ibex: Fix wishbone address semantics #5

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Merged
DawidPietrykowski merged 1 commit into from
Feb 6, 2025
Merged

cpu_ibex: Fix wishbone address semantics #5

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3 changes: 2 additions & 1 deletion samples/cpu_ibex/sim_ibex.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7,9 +7,9 @@ void IbexBusInterface::connect(WishboneInitiator<uint32_t, uint32_t> &wishbone)
wishbone.wb_ack = &rvalid_i();
wishbone.wb_rd_dat = &rdata_i();
wishbone.wb_stb = &req_o();
wishbone.wb_addr = &addr_o();
wishbone.wb_wr_dat = &wdata_o();
wishbone.wb_we = &we_o();
wishbone.wb_addr = &wb_addr;
wishbone.wb_cyc = &wb_cyc;
wishbone.wb_sel = &wb_sel;
wishbone.wb_rst = &wb_rst;
Expand All @@ -20,6 +20,7 @@ void IbexBusInterface::convert(uint8_t clk)
{
gnt_i() = req_o() & ~wb_stall;
wb_sel = be_o();
wb_addr = addr_o() / sizeof(uint32_t);

if (wb_rst)
wb_cyc = low;
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1 change: 1 addition & 0 deletions samples/cpu_ibex/sim_ibex.h
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ struct IbexBusInterface
void connect(WishboneInitiator<uint32_t, uint32_t> &wishbone);
void convert(uint8_t clk);

uint32_t wb_addr;
uint8_t wb_cyc = 0, wb_sel, wb_rst = high, wb_stall = high;
};

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