UDS program with ROM

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-0a3a23327ff67d384cf75ae5761190db5d8252c350d0a8eecdeeada093720de6923d77a3ef035e3ec727863267698c1f
+70004db2e8aaf66c8339f9101ff7156d8a38460f5e70f620aaf3d941fc0a80e20075da07b969e20c5d9fc99584f35d05

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1741212503
+1741291916

src/fuse_ctrl/rtl/fc_access_control_table.sv

@@ -24,7 +24,7 @@
 typedef struct packed {
   logic [31:0] lower_addr;  // Lower bound of the address range
   logic [31:0] upper_addr;  // Upper bound of the address range
-  logic [3:0]  axi_user_id; // AXI user ID allowed to write
+  logic [31:0]  axi_user_id; // AXI user ID allowed to write
 } access_control_entry_t;
 
 localparam int FC_TABLE_NUM_RANGES = 2;

src/integration/config/compile.yml

@@ -54,6 +54,7 @@ requires:
   - caliptra_ss_top_defines
   - axi_mem_pkg
   - caliptra_ss_top
+  - lc_ctrl
   - caliptra_top_tb_pkg
   - avery_vip
 targets:

src/integration/test_suites/caliptra_ss_jtag_uds_prog/caliptra_ss_jtag_uds_prog.c

@@ -0,0 +1,100 @@
+/*
+    Run this test with the following command
+    submit_i cpt_build2 -tc caliptra_ss_jtag_uds_prog -op -to 5000000
+    or 
+    submit_i cpt_build -tc caliptra_ss_jtag_uds_prog -op -to 5000000
+*/
+
+
+
+
+#include "soc_address_map.h"
+#include "printf.h"
+#include "riscv_hw_if.h"
+#include "soc_ifc.h"
+#include "fuse_ctrl_address_map.h"
+#include "caliptra_ss_lc_ctrl_address_map.h"
+#include <string.h>
+#include <stdint.h>
+#include <time.h>
+#include <stdlib.h>
+
+volatile char* stdout = (char *)0x21000410;
+#ifdef CPT_VERBOSITY
+    enum printf_verbosity verbosity_g = CPT_VERBOSITY;
+#else
+    enum printf_verbosity verbosity_g = LOW;
+#endif
+
+
+
+
+void main (void) {
+    int argc=0;
+    char *argv[1];
+    enum boot_fsm_state_e boot_fsm_ps;
+    const uint32_t mbox_dlen = 64;
+    uint32_t mbox_data[] = { 0x00000000,
+                             0x11111111,
+                             0x22222222,
+                             0x33333333,
+                             0x44444444,
+                             0x55555555,
+                             0x66666666,
+                             0x77777777,
+                             0x88888888,
+                             0x99999999,
+                             0xaaaaaaaa,
+                             0xbbbbbbbb,
+                             0xcccccccc,
+                             0xdddddddd,
+                             0xeeeeeeee,
+                             0xffffffff };
+    uint32_t mbox_resp_dlen;
+    uint32_t mbox_resp_data;
+    uint32_t cptra_boot_go;
+    // VPRINTF(LOW, "=================\nMCU Caliptra Boot Go\n=================\n\n")
+
+    // Writing to Caliptra Boot GO register of MCI for CSS BootFSM to bring Caliptra out of reset 
+    // This is just to see CSSBootFSM running correctly
+    lsu_write_32(SOC_MCI_REG_CPTRA_BOOT_GO, 1);
+    VPRINTF(LOW, "MCU: Writing MCI SOC_MCI_REG_CALIPTRA_BOOT_GO\n");
+
+    cptra_boot_go = lsu_read_32(SOC_MCI_REG_CPTRA_BOOT_GO);
+    VPRINTF(LOW, "MCU: Reading SOC_MCI_REG_CALIPTRA_BOOT_GO %x\n", cptra_boot_go);
+
+    ////////////////////////////////////
+    // Fuse and Boot Bringup
+    //
+    // Wait for ready_for_fuses
+    while(!(lsu_read_32(SOC_SOC_IFC_REG_CPTRA_FLOW_STATUS) & SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_FUSES_MASK));
+
+    // Initialize fuses
+    lsu_write_32(SOC_SOC_IFC_REG_CPTRA_FUSE_WR_DONE, SOC_IFC_REG_CPTRA_FUSE_WR_DONE_DONE_MASK);
+    VPRINTF(LOW, "MCU: Set fuse wr done\n");
+
+
+
+    VPRINTF(LOW, "=================\n CALIPTRA_SS JTAG UDS Prov TEST with ROM \n=================\n\n");
+
+
+    for (uint32_t ii = 0; ii < 5000; ii++) {
+        __asm__ volatile ("nop"); // Sleep loop as "nop"
+    }
+
+    cptra_boot_go = 0;
+    VPRINTF(LOW, "MCU: waits in success loop\n");
+    while(cptra_boot_go != SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_MASK){
+        cptra_boot_go = lsu_read_32(SOC_SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP) & SOC_IFC_REG_SS_DBG_MANUF_SERVICE_REG_RSP_UDS_PROGRAM_SUCCESS_MASK;
+    }
+
+    cptra_boot_go = lsu_read_32(LC_CTRL_HW_REVISION0_OFFSET); // Reset the lcc and its bfm
+    VPRINTF(LOW, "LC&Fuse_CTRLis under reset!\n");
+    for (uint16_t ii = 0; ii < 5000; ii++) {
+        __asm__ volatile ("nop"); // Sleep loop as "nop"
+    }
+
+
+    SEND_STDOUT_CTRL(0xff);
+
+}

src/integration/test_suites/caliptra_ss_jtag_uds_prog/caliptra_ss_jtag_uds_prog.tcl

@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+
+
+init
+
+set script_dir [file dirname [info script]]
+source [file join $script_dir common.tcl]
+
+array set data {
+    0 0x12345678
+    1 0xABBACDDC
+    2 0xDEADBEEF
+    3 0xFEEDBABE
+    4 0xBEACCAEB
+}
+set dlen_words [array size data]
+set dlen_bytes [expr {$dlen_words * 4}]
+
+puts "Read Debug Module Status Register..."
+set val [riscv dmi_read $dmstatus_addr]
+puts "dmstatus: $val"
+if {($val & 0x00000c00) == 0} {
+    echo "The hart is halted!"
+    # shutdown error
+}
+puts ""
+
+
+# Define register addresses
+set SS_DBG_MANUF_SERVICE_REG_REQ        0x70
+set SS_DBG_MANUF_SERVICE_REG_RSP        0x71
+set DMI_REG_BOOTFSM_GO_ADDR             0x61
+
+# Write to the debug service register to trigger UDS programming.
+puts "Triggering UDS programming..."
+riscv dmi_write $SS_DBG_MANUF_SERVICE_REG_REQ 0x4
+set actual [riscv dmi_read $SS_DBG_MANUF_SERVICE_REG_REQ]
+puts "SS_DBG_MANUF_SERVICE_REG_REQ: $actual"
+
+puts "Set BOOTFSM_GO to High..."
+riscv dmi_write $DMI_REG_BOOTFSM_GO_ADDR 0x1
+
+# Polling UDS programming status
+puts "Polling UDS programming status: waiting for in-progress flag..."
+set status [riscv dmi_read $SS_DBG_MANUF_SERVICE_REG_RSP]
+puts "Expected in-progress flag (bit 9) not set initially. Waiting."
+while {([expr {$status & 0x100}] == 0)} {    
+    after 5000
+    set status [riscv dmi_read $SS_DBG_MANUF_SERVICE_REG_RSP]
+}
+
+puts "In-progress flag set. Programming complete."
+
+# Now, continuously poll until the in-progress flag clears.
+while {($status & 0x100) != 0} {
+    after 100    ;# Wait 1000ms between polls to avoid busy looping.
+    set status [riscv dmi_read $SS_DBG_MANUF_SERVICE_REG_RSP]
+}
+
+puts "UDS programming in-progress flag cleared. Evaluating result..."
+
+# After the in-progress flag is cleared, read the response register.
+set rsp_val [riscv dmi_read $SS_DBG_MANUF_SERVICE_REG_RSP]
+# Check for failure (bit 8, mask 0x80) and success (bit 7, mask 0x40).
+set failure [expr {($rsp_val & 0x80) != 0}]
+set success [expr {($rsp_val & 0x40) != 0}]
+
+if {$failure} {
+    puts "UDS programming failed (failure bit set)."
+    shutdown error
+} elseif {$success} {
+    puts "UDS programming succeeded (success bit set)."
+} else {
+    puts "UDS programming returned an unexpected status: $rsp_val"
+    shutdown error
+}
+
+puts "UDS programming completed successfully."
+
+puts "Put JTAG into a infinite loop!!!"
+while {([expr {$status & 0x100}] == 0)} {    
+    after 5000
+    set status [riscv dmi_read $SS_DBG_MANUF_SERVICE_REG_RSP]
+}
+shutdown
+

src/integration/test_suites/caliptra_ss_jtag_uds_prog/caliptra_ss_jtag_uds_prog.yml

@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+seed: 1
+testname: caliptra_ss_jtag_uds_prog

src/integration/test_suites/caliptra_ss_jtag_uds_prog/common.tcl

@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+proc compare {x y} {
+    puts "'$x' vs. '$y'"
+
+    if {[llength $y] != [llength $y]} {
+        puts "length mismatch!"
+        return -1
+    }
+
+    for {set i 0} {$i < [llength $x]} {incr i} {
+        if {[lindex $x $i] != [lindex $y $i]} {
+            puts "item $i mismatch!"
+            return -1
+        }
+    }
+
+    return 0
+}
+
+set STDOUT 0x300300cc
+
+set mbox_clk_gate_en 0xf2
+set mbox_lock_debug 0xf9
+set mbox_unlock_debug 0xfa
+
+set mbox_lock_mem_addr 0x30020000
+set mbox_user_mem_addr 0x30020004
+set mbox_cmd_mem_addr 0x30020008
+set mbox_dlen_mem_addr 0x3002000C
+set mbox_datain_mem_addr 0x30020010
+set mbox_dataout_mem_addr 0x30020014
+set mbox_execute_mem_addr 0x30020018
+set mbox_status_mem_addr 0x3002001C
+set mbox_unlock_mem_addr 0x30020020
+
+set mbox_dlen_dmi_addr 0x50
+set mbox_dout_dmi_addr 0x51
+set mbox_status_dmi_addr 0x52
+
+set dmstatus_addr 0x11
+

src/integration/testbench/caliptra_ss_top_tb.sv

@@ -1536,6 +1536,26 @@ module caliptra_ss_top_tb
         cptra_ss_FIPS_ZEROIZATION_PPD_i = 1'b0;
     end
 
+    `include "caliptra_ss_includes.svh"
+    logic [$bits(lc_ctrl_state_pkg::lc_state_t)-1:0] MANUF_state;
+    assign MANUF_state = lc_ctrl_state_pkg::lc_state_t'(lc_ctrl_state_pkg::LcStDev);
+    initial begin
+        if ($test$plusargs("CALIPTRA_SS_UDS_PROG")) begin
+            force caliptra_ss_dut.mci_top_i.from_otp_to_lcc_program_i.state = MANUF_state;
+            force cptra_ss_cptra_core_m_axi_if.awuser = CPTRA_SS_STRAP_CLPTRA_CORE_AXI_USER;
+            force cptra_ss_cptra_core_bootfsm_bp_i = 1'b1;
+            force caliptra_ss_dut.caliptra_top_dut.soc_ifc_top1.soc_ifc_reg_hwif_in.CPTRA_HW_CONFIG.SUBSYSTEM_MODE_en.next = 1'b1;
+            $monitor("CALIPTRA_SS_UDS_PROG: UDS_REQ is %x\n",caliptra_ss_dut.caliptra_top_dut.soc_ifc_top1.soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_REQ.UDS_PROGRAM_REQ.value);
+            $monitor("CALIPTRA_SS_UDS_PROG: UDS_RESP IN PROGRESS is %x\n",caliptra_ss_dut.caliptra_top_dut.soc_ifc_top1.soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_IN_PROGRESS);
+            $monitor("CALIPTRA_SS_UDS_PROG: UDS_RESP UDS_PROGRAM_FAIL is %x\n",caliptra_ss_dut.caliptra_top_dut.soc_ifc_top1.soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_FAIL);
+            $monitor("CALIPTRA_SS_UDS_PROG: UDS_RESP UDS_PROGRAM_SUCCESS is %x\n",caliptra_ss_dut.caliptra_top_dut.soc_ifc_top1.soc_ifc_reg_hwif_out.SS_DBG_MANUF_SERVICE_REG_RSP.UDS_PROGRAM_SUCCESS);
+            $monitor("CALIPTRA_SS_UDS_PROG: BootFSM_GO is %x\n",caliptra_ss_dut.caliptra_top_dut.soc_ifc_top1.soc_ifc_reg_hwif_out.CPTRA_BOOTFSM_GO);
+            $monitor("CALIPTRA_SS_UDS_PROG: BootFSM_BrkPoint_Latched is %x\n",caliptra_ss_dut.caliptra_top_dut.soc_ifc_top1.BootFSM_BrkPoint_Latched);
+            $monitor("CALIPTRA_SS_UDS_PROG: CPTRA_FLOW_STATUS is %x\n",caliptra_ss_dut.caliptra_top_dut.soc_ifc_top1.soc_ifc_reg_hwif_in.CPTRA_FLOW_STATUS);
+        end 
+    end
+
+
 `ifdef LCC_FC_BFM_SIM
 
     always_comb begin
@@ -1705,8 +1725,8 @@ module caliptra_ss_top_tb
     assign cptra_ss_strap_caliptra_base_addr_i  = 64'hba5e_ba11;
     assign cptra_ss_strap_mci_base_addr_i       = 64'h0;
     assign cptra_ss_strap_recovery_ifc_base_addr_i = {32'h0, `SOC_I3CCSR_I3C_EC_START};
-    assign cptra_ss_strap_otp_fc_base_addr_i    = 64'h0;
-    assign cptra_ss_strap_uds_seed_base_addr_i  = 64'h0;
+    assign cptra_ss_strap_otp_fc_base_addr_i    = 64'h0000_0000_7000_0000;
+    assign cptra_ss_strap_uds_seed_base_addr_i  = 64'h0000_0000_0000_0000;
     assign cptra_ss_strap_prod_debug_unlock_auth_pk_hash_reg_bank_offset_i = 32'h0;
     assign cptra_ss_strap_num_of_prod_debug_unlock_auth_pk_hashes_i        = 32'h0;
     assign cptra_ss_strap_caliptra_dma_axi_user_i = CPTRA_SS_STRAP_CLPTRA_CORE_AXI_USER;

tools/scripts/fc_access_control_table.py

@@ -84,7 +84,7 @@ def generate_sv(entries):
         "typedef struct packed {\n"
         "  logic [31:0] lower_addr;  // Lower bound of the address range\n"
         "  logic [31:0] upper_addr;  // Upper bound of the address range\n"
-        "  logic [3:0]  axi_user_id; // AXI user ID allowed to write\n"
+        "  logic [31:0]  axi_user_id; // AXI user ID allowed to write\n"
         "} access_control_entry_t;\n\n"
         "localparam int FC_TABLE_NUM_RANGES = %d;\n\n" % num_entries +
         "localparam access_control_entry_t access_control_table [FC_TABLE_NUM_RANGES] = '{\n"