moved prim generic to ss_tb

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-75d107d8a7cd73840953158cbfd9daefa9817cce6ce512c1b022ebc78bb57abd525eaef6822f2e7ec4277e5a5fcae33c
+3292dba61c9f9345bda4426946196fc4ee56bfe93177a5f556fae6b33e92e4300cb279174fb9589ab7795bc97ddf8f83

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1742860813
+1742864248

src/fuse_ctrl/config/compile.yml

@@ -4,6 +4,7 @@ schema_version: 2.4.0
 requires:
   - caliptra_prim
   - lc_ctrl_pkg
+  - ast_pkg
 targets:
   rtl:
     directories: [$COMPILE_ROOT/rtl]
@@ -46,7 +47,7 @@ targets:
       - $COMPILE_ROOT/rtl/otp_ctrl_part_unbuf.sv
       - $COMPILE_ROOT/rtl/otp_ctrl_scrmbl.sv
       - $COMPILE_ROOT/rtl/otp_ctrl_token_const.sv
-      - $COMPILE_ROOT/rtl/prim_generic_otp.sv
+      # - $COMPILE_ROOT/rtl/prim_generic_otp.sv
       - $COMPILE_ROOT/rtl/otp_ctrl.sv
       #- $COMPILE_ROOT/rtl/otp_ctrl_top.sv
     tops: [otp_ctrl]

src/fuse_ctrl/rtl/otp_ctrl.sv

@@ -50,6 +50,9 @@ module otp_ctrl
   input  tlul_pkg::tl_h2d_t                          prim_tl_i,
   output tlul_pkg::tl_d2h_t                          prim_tl_o,
 
+  input prim_generic_otp_outputs_t                  prim_generic_otp_outputs_i,
+  output prim_generic_otp_inputs_t                  prim_generic_otp_inputs_o,
+
   // Interrupt Requests
   output logic                                       intr_otp_operation_done_o,
   output logic                                       intr_otp_error_o,
@@ -897,53 +900,47 @@ end
   assign cio_test_en_o = (lc_ctrl_pkg::lc_tx_test_true_strict(lc_dft_en[2])) ?
                          {OtpTestVectWidth{1'b1}} : '0;
 
-  // SEC_CM: MACRO.MEM.CM, MACRO.MEM.INTEGRITY
-  prim_generic_otp #(
-    .Width            ( OtpWidth            ),
-    .Depth            ( OtpDepth            ),
-    .SizeWidth        ( OtpSizeWidth        ),
-    .PwrSeqWidth      ( OtpPwrSeqWidth      ),
-    .TestCtrlWidth    ( OtpTestCtrlWidth    ),
-    .TestStatusWidth  ( OtpTestStatusWidth  ),
-    .TestVectWidth    ( OtpTestVectWidth    ),
-    .MemInitFile      ( MemInitFile         ),
-    .VendorTestOffset ( VendorTestOffset    ),
-    .VendorTestSize   ( VendorTestSize      )
-  ) u_otp (
-    .clk_i,
-    .rst_ni,
-    // Observability controls to/from AST
-    .obs_ctrl_i,
-    .otp_obs_o,
-    // Power sequencing signals to/from AST
-    .pwr_seq_o        ( otp_ast_pwr_seq_o.pwr_seq     ),
-    .pwr_seq_h_i      ( otp_ast_pwr_seq_h_i.pwr_seq_h ),
-    .ext_voltage_io   ( otp_ext_voltage_h_io          ),
-    // Test interface
-    .test_ctrl_i      ( lc_otp_vendor_test_i.ctrl     ),
-    .test_status_o    ( lc_otp_vendor_test_o.status   ),
-    .test_vect_o      ( otp_test_vect                 ),
-    .test_tl_i        ( prim_tl_h2d_gated             ),
-    .test_tl_o        ( prim_tl_d2h_gated             ),
+
+  always_comb begin : FCM_port_assignment
+    // Clock, reset and observability
+    prim_generic_otp_inputs_o.clk_i      = clk_i;
+    prim_generic_otp_inputs_o.rst_ni     = rst_ni;
+    prim_generic_otp_inputs_o.obs_ctrl_i = obs_ctrl_i;
+    otp_obs_o                          = prim_generic_otp_outputs_i.otp_obs_o;
+
+    // Power sequencing signals
+    prim_generic_otp_inputs_o.pwr_seq_h_i = otp_ast_pwr_seq_h_i.pwr_seq_h;
+    otp_ast_pwr_seq_o.pwr_seq            = prim_generic_otp_outputs_i.pwr_seq_o;
+
+    // Test interface signals
+    lc_otp_vendor_test_o.status          = '0;
+    otp_test_vect                        = '0;
+    prim_tl_d2h_gated                    = '0;
+
     // Other DFT signals
-    .scan_en_i,
-    .scan_rst_ni,
-    .scanmode_i,
-    // Alerts
-    .fatal_alert_o    ( fatal_prim_otp_alert ),
-    .recov_alert_o    ( recov_prim_otp_alert ),
-    // Read / Write command interface
-    .ready_o          ( otp_prim_ready       ),
-    .valid_i          ( otp_prim_valid       ),
-    .cmd_i            ( otp_arb_bundle.cmd   ),
-    .size_i           ( otp_arb_bundle.size  ),
-    .addr_i           ( otp_arb_bundle.addr  ),
-    .wdata_i          ( otp_arb_bundle.wdata ),
-    // Read data out
-    .valid_o          ( otp_rvalid           ),
-    .rdata_o          ( part_otp_rdata       ),
-    .err_o            ( part_otp_err         )
-  );
+    prim_generic_otp_inputs_o.scanmode_i  = scanmode_i;
+    prim_generic_otp_inputs_o.scan_en_i   = scan_en_i;
+    prim_generic_otp_inputs_o.scan_rst_ni = scan_rst_ni;
+
+    // Command interface (read/write)
+    prim_generic_otp_inputs_o.valid_i  = otp_prim_valid;
+    prim_generic_otp_inputs_o.size_i   = otp_arb_bundle.size;
+    prim_generic_otp_inputs_o.cmd_i    = otp_arb_bundle.cmd;
+    prim_generic_otp_inputs_o.addr_i   = otp_arb_bundle.addr;
+    prim_generic_otp_inputs_o.wdata_i  = otp_arb_bundle.wdata;
+
+    // Ready/Response signals
+    otp_prim_ready      = prim_generic_otp_outputs_i.ready_o;
+    otp_rvalid          = prim_generic_otp_outputs_i.valid_o;
+    part_otp_rdata      = prim_generic_otp_outputs_i.rdata_o;
+    part_otp_err        = prim_generic_otp_outputs_i.err_o;
+
+    // Alert signals
+    fatal_prim_otp_alert = prim_generic_otp_outputs_i.fatal_alert_o;
+    recov_prim_otp_alert = prim_generic_otp_outputs_i.recov_alert_o;
+  end
+
+
 
   logic otp_fifo_valid;
   logic [vbits(NumAgents)-1:0] otp_part_idx;

src/fuse_ctrl/rtl/otp_ctrl_pkg.sv

@@ -7,6 +7,7 @@ package otp_ctrl_pkg;
 
   import caliptra_prim_util_pkg::vbits;
   import otp_ctrl_reg_pkg::*;
+  import ast_pkg::*;
 
   ////////////////////////
   // General Parameters //
@@ -354,4 +355,52 @@ package otp_ctrl_pkg;
     '{ lower_addr: 32'h00000088, upper_addr: 32'h0000FFFF} // MCU core
   };
 
+    //------------------------------------------------------------------
+    // Typedef for PRIM GENERIC Module Inputs
+    //------------------------------------------------------------------
+    typedef struct packed {
+      // Clock, reset, and observability
+      logic                         clk_i;
+      logic                         rst_ni;
+      ast_pkg::ast_obs_ctrl_t       obs_ctrl_i;
+
+      // Power sequencing (input from host)
+      logic [OtpPwrSeqWidth-1:0]       pwr_seq_h_i;
+
+
+      // DFT signals
+      caliptra_prim_mubi_pkg::mubi4_t scanmode_i;
+      logic                         scan_en_i;
+      logic                         scan_rst_ni;
+
+      // Ready/valid handshake and command channel
+      logic                            valid_i;
+      logic [OtpSizeWidth-1:0]         size_i;   // (Native words)-1
+      caliptra_prim_otp_pkg::cmd_e     cmd_i;
+      logic [OtpAddrWidth-1:0]         addr_i;
+      logic [OtpIfWidth-1:0]           wdata_i;
+    } prim_generic_otp_inputs_t;
+
+    //------------------------------------------------------------------
+    // Typedef for PRIM GENERIC Module Outputs
+    //------------------------------------------------------------------
+    typedef struct packed {
+      // Observability output
+      logic [7:0]                 otp_obs_o;
+
+      // Power sequencing output
+      logic [OtpPwrSeqWidth-1:0]     pwr_seq_o;
+
+
+      // Alert signals
+      logic                       fatal_alert_o;
+      logic                       recov_alert_o;
+
+      // Ready/valid handshake and response channel
+      logic                       ready_o;
+      logic                       valid_o;
+      logic [OtpIfWidth-1:0]         rdata_o;
+      caliptra_prim_otp_pkg::err_e     err_o;
+    } prim_generic_otp_outputs_t;
+
 endpackage : otp_ctrl_pkg

src/integration/config/compile.yml

@@ -56,6 +56,8 @@ requires:
   - axi_mem_pkg
   - caliptra_ss_top
   - lc_ctrl
+  - ast_pkg
+  - fuse_ctrl_pkg
   - caliptra_top_tb_pkg
   - avery_vip
 targets:
@@ -78,6 +80,7 @@ targets:
       - $COMPILE_ROOT/testbench/aaxi_pkg_caliptra_test.sv
       - $COMPILE_ROOT/testbench/aaxi4_interconnect.sv
       - $COMPILE_ROOT/testbench/fuse_ctrl_bfm.sv
+      - $COMPILE_ROOT/testbench/prim_generic_otp.sv
       - $COMPILE_ROOT/testbench/lc_ctrl_bfm.sv
       - $COMPILE_ROOT/testbench/caliptra_ss_tb_cmd_list.svh
       - $COMPILE_ROOT/testbench/fc_lcc_tb_services.sv

src/integration/rtl/caliptra_ss_top.sv

@@ -187,8 +187,8 @@ module caliptra_ss_top
     output wire cptra_ss_soc_hw_debug_en_o,
 
 // Caliptra SS Fuse Controller Interface (Fuse Macros)
-    input  tlul_pkg::tl_h2d_t                          cptra_ss_fuse_macro_prim_tl_i,
-    output tlul_pkg::tl_d2h_t                          cptra_ss_fuse_macro_prim_tl_o,
+    input otp_ctrl_pkg::prim_generic_otp_outputs_t      cptra_ss_fuse_macro_outputs_i,
+    output otp_ctrl_pkg::prim_generic_otp_inputs_t      cptra_ss_fuse_macro_inputs_o,
 
 // Caliptra SS I3C GPIO Interface
 `ifdef DIGITAL_IO_I3C
@@ -1365,8 +1365,10 @@ module caliptra_ss_top
         .core_axi_rd_req            (cptra_ss_otp_core_axi_rd_req_i),
         .core_axi_rd_rsp            (cptra_ss_otp_core_axi_rd_rsp_o),
 
-        .prim_tl_i                  (cptra_ss_fuse_macro_prim_tl_i),
-        .prim_tl_o                  (cptra_ss_fuse_macro_prim_tl_o),
+        .prim_tl_i                  ('0),
+        .prim_tl_o                  (),
+        .prim_generic_otp_outputs_i (cptra_ss_fuse_macro_outputs_i),
+        .prim_generic_otp_inputs_o  (cptra_ss_fuse_macro_inputs_o),
 
         .intr_otp_operation_done_o  (intr_otp_operation_done),
         .intr_otp_error_o           (fc_intr_otp_error), //TODO: This signal should be connected to MCI

src/integration/test_suites/libs/lc_ctrl/lc_ctrl.h

@@ -49,7 +49,7 @@ typedef enum {
 } lc_state_dec_t;
 
 void lcc_initialization(void);
-
+void force_lcc_tokens(void);
 void sw_transition_req(uint32_t next_lc_state,
                         uint32_t token_31_0,
                         uint32_t token_63_32,
@@ -60,7 +60,6 @@ void sw_transition_req(uint32_t next_lc_state,
 uint32_t calc_lc_state_mnemonic(uint32_t state);
 void transition_state(uint32_t next_lc_state, uint32_t token_31_0, uint32_t token_63_32, uint32_t token_95_64, uint32_t token_127_96, uint32_t conditional);
 void test_all_lc_transitions_no_RMA_no_SCRAP(void);
-void test_all_lc_transitions_no_RMA_no_SCRAP(void);
 void sw_transition_req_with_expec_error(uint32_t next_lc_state,
     uint32_t token_31_0,
     uint32_t token_63_32,

src/integration/testbench/caliptra_ss_top_tb.sv

@@ -1577,6 +1577,14 @@ module caliptra_ss_top_tb
         .rdata_o (        )
     );
 
+
+  //-------------------------------------------------------------------------
+  // Aggregated signals for the OTP macro interface.
+  // These signals will connect both to caliptra_ss_top ports and to prim_generic_otp.
+  //-------------------------------------------------------------------------
+  otp_ctrl_pkg::prim_generic_otp_outputs_t cptra_ss_fuse_macro_outputs_tb;
+  otp_ctrl_pkg::prim_generic_otp_inputs_t  cptra_ss_fuse_macro_inputs_tb;
+
    // driven by lc_ctrl_bfm
    logic cptra_ss_lc_esclate_scrap_state0_i;
    logic cptra_ss_lc_esclate_scrap_state1_i;
@@ -1629,6 +1637,48 @@ module caliptra_ss_top_tb
         .fuse_ctrl_rdy       (fuse_ctrl_rdy       )
     );
 
+
+    prim_generic_otp #(
+        .Width            ( otp_ctrl_pkg::OtpWidth            ),
+        .Depth            ( otp_ctrl_pkg::OtpDepth            ),
+        .SizeWidth        ( otp_ctrl_pkg::OtpSizeWidth        ),
+        .PwrSeqWidth      ( otp_ctrl_pkg::OtpPwrSeqWidth      ),
+        .TestCtrlWidth    ( otp_ctrl_pkg::OtpTestCtrlWidth    ),
+        .TestStatusWidth  ( otp_ctrl_pkg::OtpTestStatusWidth  ),
+        .TestVectWidth    ( otp_ctrl_pkg::OtpTestVectWidth    ),
+        .MemInitFile      ("otp-img.2048.vmem"                  ),
+        .VendorTestOffset ( otp_ctrl_reg_pkg::VendorTestOffset    ),
+        .VendorTestSize   ( otp_ctrl_reg_pkg::VendorTestSize      )
+    ) u_otp (
+        // Clock and Reset
+        .clk_i          ( cptra_ss_fuse_macro_inputs_tb.clk_i ),
+        .rst_ni         ( cptra_ss_fuse_macro_inputs_tb.rst_ni ),
+        // Observability controls to/from AST
+        .obs_ctrl_i     ( cptra_ss_fuse_macro_inputs_tb.obs_ctrl_i ),
+        .otp_obs_o      ( cptra_ss_fuse_macro_outputs_tb.otp_obs_o ),
+        // Power sequencing signals to/from AST
+        .pwr_seq_o      ( cptra_ss_fuse_macro_outputs_tb.pwr_seq_o ),
+        .pwr_seq_h_i    ( cptra_ss_fuse_macro_inputs_tb.pwr_seq_h_i ),
+        // Other DFT signals
+        .scanmode_i     ( cptra_ss_fuse_macro_inputs_tb.scanmode_i ),
+        .scan_en_i      ( cptra_ss_fuse_macro_inputs_tb.scan_en_i ),
+        .scan_rst_ni    ( cptra_ss_fuse_macro_inputs_tb.scan_rst_ni ),
+        // Alert signals
+        .fatal_alert_o  ( cptra_ss_fuse_macro_outputs_tb.fatal_alert_o ),
+        .recov_alert_o  ( cptra_ss_fuse_macro_outputs_tb.recov_alert_o ),
+        // Ready/valid handshake and command interface
+        .ready_o        ( cptra_ss_fuse_macro_outputs_tb.ready_o ),
+        .valid_i        ( cptra_ss_fuse_macro_inputs_tb.valid_i ),
+        .size_i         ( cptra_ss_fuse_macro_inputs_tb.size_i ),
+        .cmd_i          ( cptra_ss_fuse_macro_inputs_tb.cmd_i ),
+        .addr_i         ( cptra_ss_fuse_macro_inputs_tb.addr_i ),
+        .wdata_i        ( cptra_ss_fuse_macro_inputs_tb.wdata_i ),
+        // Response channel
+        .valid_o        ( cptra_ss_fuse_macro_outputs_tb.valid_o ),
+        .rdata_o        ( cptra_ss_fuse_macro_outputs_tb.rdata_o ),
+        .err_o          ( cptra_ss_fuse_macro_outputs_tb.err_o )
+    );
+
     // --- I3C env and interface ---
     ai3c_env i3c_env0;
     wand  SCL;
@@ -1898,8 +1948,8 @@ module caliptra_ss_top_tb
         .cptra_ss_soc_dft_en_o,
         .cptra_ss_soc_hw_debug_en_o,
 
-        .cptra_ss_fuse_macro_prim_tl_i('0),
-        .cptra_ss_fuse_macro_prim_tl_o(),
+        .cptra_ss_fuse_macro_outputs_i (cptra_ss_fuse_macro_outputs_tb),
+        .cptra_ss_fuse_macro_inputs_o  (cptra_ss_fuse_macro_inputs_tb),
 
     // I3C Interface
     `ifdef DIGITAL_IO_I3C

src/fuse_ctrl/rtl/prim_generic_otp.sv → src/integration/testbench/prim_generic_otp.sv

@@ -34,14 +34,6 @@ module prim_generic_otp
   // Macro-specific power sequencing signals to/from AST
   output logic [PwrSeqWidth-1:0] pwr_seq_o,
   input        [PwrSeqWidth-1:0] pwr_seq_h_i,
-  // External programming voltage
-  inout wire                     ext_voltage_io,
-  // Test interfaces
-  input        [TestCtrlWidth-1:0]   test_ctrl_i,
-  output logic [TestStatusWidth-1:0] test_status_o,
-  output logic [TestVectWidth-1:0]   test_vect_o,
-  input  tlul_pkg::tl_h2d_t          test_tl_i,
-  output tlul_pkg::tl_d2h_t          test_tl_o,
   // Other DFT signals
   input caliptra_prim_mubi_pkg::mubi4_t   scanmode_i,  // Scan Mode input
   input                          scan_en_i,   // Scan Shift
@@ -80,10 +72,6 @@ module prim_generic_otp
   assign unused_obs = |obs_ctrl_i;
   assign otp_obs_o = '0;
 
-  wire unused_ext_voltage;
-  assign unused_ext_voltage = ext_voltage_io;
-  logic unused_test_ctrl_i;
-  assign unused_test_ctrl_i = ^test_ctrl_i;
 
   logic unused_scan;
   assign unused_scan = ^{scanmode_i, scan_en_i, scan_rst_ni};
@@ -92,8 +80,7 @@ module prim_generic_otp
   assign fatal_alert_o = intg_err || fsm_err;
   assign recov_alert_o = 1'b0;
 
-  assign test_vect_o = '0;
-  assign test_status_o = '0;
+
 
   ////////////////////////////////////
   // TL-UL Test Interface Emulation //
@@ -104,8 +91,8 @@ module prim_generic_otp
   otp_ctrl_prim_reg_top u_reg_top (
     .clk_i,
     .rst_ni,
-    .tl_i      (test_tl_i ),
-    .tl_o      (test_tl_o ),
+    .tl_i      ('0 ),
+    .tl_o      ( ),
     .reg2hw    (reg2hw    ),
     .hw2reg    (hw2reg    ),
     .intg_err_o(intg_err  )