[RTL, RDL, DOC] add aggregate error register connections at ss top

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docs/CaliptraSSHardwareSpecification.md

@@ -1321,6 +1321,22 @@ MCI aggregates the error information (Fatal, Non-Fatal errors from Caliptra, any
 
 ![](images/MCI-error-agg.png)
 
+Aggregate error register assignments are documented in the register specification: **TODO:** Add a link to rdl -> html file
+
+Regions of 6 bits in the aggregate error registers are reserved for each component.
+MCU and Caliptra errors are connected to appropriate severity levels.
+Lifecycle controller, fuse controller and I3C are connected to both severities. 
+Masks are used to set the severity of each error for these components. These can be configured by integrators, ROM, or runtime firmware.
+
+| **Error Register Bits** | **Component**         | **Default Error Severity** | **Description**          |
+| :---------              | :---------            | :---------                 |:---------                |
+| Aggregate error[5:0]    | Caliptra core         | Both                       | [Caliptra errors](https://github.com/chipsalliance/Caliptra/blob/main/doc/Caliptra.md#error-reporting-and-handling) |
+| Aggregate error[11:6]   | MCU                   | Both                       | DCCM double bit ECC error is fatal <br> DCCM single bit ECC error is non-fatal |
+| Aggregate error[17:12]  | Life cycle controller | Fatal                      | [LCC alerts](https://opentitan.org/book/hw/ip/lc_ctrl/doc/interfaces.html#security-alerts) |
+| Aggregate error[23:18]  | OTP Fuse controller   | Fatal                      | [FC alerts](https://opentitan.org/book/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/interfaces.html#security-alerts) |
+| Aggregate error[29:24]  | I3C                   | Non-Fatal                  | Peripheral reset and escalated reset pins from I3C <br> **TODO:** Add a link to I3C doc |
+| Aggregate error[31:30]  | Spare bits            | None                       | Spare bits for integrator use |
+
 MCI also generates error signals for its own internal blocks, specifically for MCU SRAM & mailboxes double bit ECC and WDT.
 
 ![](images/MCI-internal-error.png)

src/integration/rtl/caliptra_ss_top.sv

@@ -245,8 +245,16 @@ module caliptra_ss_top
 );
 
     logic [pt.PIC_TOTAL_INT:1]  ext_int;
+    logic        [31:0]         agg_error_fatal;
+    logic        [31:0]         agg_error_non_fatal;
     logic                       timer_int;
 
+    logic                       mcu_dccm_ecc_single_error;
+    logic                       mcu_dccm_ecc_double_error;
+
+    logic                       i3c_peripheral_reset;
+    logic                       i3c_escalated_reset;
+
     logic        [31:0]         reset_vector;
 
 
@@ -748,6 +756,21 @@ module caliptra_ss_top
     assign ext_int[`VEER_INTR_VEC_FC]                   = intr_otp_operation_done;
     assign ext_int[pt.PIC_TOTAL_INT:`VEER_INTR_EXT_LSB] = cptra_ss_mcu_ext_int;
 
+    //Aggregate error connections
+    assign agg_error_fatal[5:0]   = {5'b0, cptra_error_fatal}; //CPTRA
+    assign agg_error_fatal[11:6]  = {5'b0, mcu_dccm_ecc_double_error}; //MCU
+    assign agg_error_fatal[17:12] = {{6-lc_ctrl_reg_pkg::NumAlerts{1'b0}}, lc_alerts_o}; //LCC
+    assign agg_error_fatal[23:18] = {{6-otp_ctrl_reg_pkg::NumAlerts{1'b0}}, fc_alerts}; //FC
+    assign agg_error_fatal[29:24] = {4'b0, i3c_peripheral_reset, i3c_escalated_reset}; //I3C
+    assign agg_error_fatal[31:30] = '0; //spare
+
+    assign agg_error_non_fatal[5:0]   = {5'b0, cptra_error_non_fatal}; //CPTRA
+    assign agg_error_non_fatal[11:6]  = {5'b0, mcu_dccm_ecc_single_error}; //MCU
+    assign agg_error_non_fatal[17:12] = {{6-lc_ctrl_reg_pkg::NumAlerts{1'b0}}, lc_alerts_o}; //LCC
+    assign agg_error_non_fatal[23:18] = {{6-otp_ctrl_reg_pkg::NumAlerts{1'b0}}, fc_alerts}; //FC
+    assign agg_error_non_fatal[29:24] = {4'b0, i3c_peripheral_reset, i3c_escalated_reset}; //I3C
+    assign agg_error_non_fatal[31:30] = '0; //spare
+
     //=========================================================================-
     // MCU instance
     //=========================================================================-
@@ -1023,8 +1046,8 @@ module caliptra_ss_top
 
         .iccm_ecc_single_error  (),
         .iccm_ecc_double_error  (),
-        .dccm_ecc_single_error  (),
-        .dccm_ecc_double_error  (),
+        .dccm_ecc_single_error  (mcu_dccm_ecc_single_error),
+        .dccm_ecc_double_error  (mcu_dccm_ecc_double_error),
 
         .core_id                ('0),
         .scan_mode              ( 1'b0 ),        // To enable scan mode
@@ -1100,9 +1123,9 @@ module caliptra_ss_top
 `endif
         .recovery_payload_available_o(payload_available_o),
         .recovery_image_activated_o(image_activated_o),
-        .peripheral_reset_o(),
+        .peripheral_reset_o(i3c_peripheral_reset),
         .peripheral_reset_done_i(1'b1),
-        .escalated_reset_o(),
+        .escalated_reset_o(i3c_escalated_reset),
         .irq_o()
 
     // TODO: Add interrupts
@@ -1168,8 +1191,8 @@ module caliptra_ss_top
         // -- connects to ss_generic_fw_exec_ctrl (bit 2)
         .mcu_sram_fw_exec_region_lock(cptra_ss_cptra_generic_fw_exec_ctrl_2_mcu_i),
 
-        .agg_error_fatal('0),       // FIXME connect to internal IPs
-        .agg_error_non_fatal('0),   // FIXME connect to internal IPs
+        .agg_error_fatal(agg_error_fatal),
+        .agg_error_non_fatal(agg_error_non_fatal),
 
         .all_error_fatal(cptra_ss_all_error_fatal_o),
         .all_error_non_fatal(cptra_ss_all_error_non_fatal_o),

src/mci/rtl/mci_reg.rdl

@@ -233,6 +233,17 @@ addrmap mci_reg {
                 mask register. After the output interrupt is asserted, clearing
                 the bit in this register will not cause the interrupt to deassert.
                 Only an MCI reset will clear the fatal error interrupt.
+                [br] 5:0 -- caliptra core fatal errors
+                [br] {5'b0, cptra_error_fatal}
+                [br] 11:6 - mcu fatal errors
+                [br] {5'b0, mcu_dccm_ecc_double_error}
+                [br] 17:12 -- lcc alerts
+                [br] {3'b0, fatal_bus_integ_error, fatal_state_error, fatal_prog_error}
+                [br] 23:18 -- otp fc alerts
+                [br] {1'b0, recov_prim_otp_alert, fatal_prim_otp_alert, fatal_bus_integ_error, fatal_check_error, fatal_macro_error}
+                [br] 29:24 -- I3C - masked by default, unmasked in non_fatal error register
+                [br] {4'b0, i3c_peripheral_reset, i3c_escalated_reset}
+                [br] 31:30 -- spare bits
                 [br]AXI Access: RW1C
                 [br]TAP Access [with debug intent set]: RO";
         rw_rw_sticky_hw agg_error_fatal31 = 1'b0;
@@ -304,14 +315,17 @@ addrmap mci_reg {
                 that firmware may cause the mci_error_non_fatal signal to deassert by
                 writing to any of these registers, if the write results in all error
                 bits being cleared or masked:
-                [br][list]
-                [br] [*] HW_ERROR_NON_FATAL
-                [br] [*] AGG_ERROR_NON_FATAL
-                [br] [*] FW_ERROR_NON_FATAL
-                [br] [*] hw_error_non_fatal_mask
-                [br] [*] agg_error_non_fatal_mask
-                [br] [*] fw_error_non_fatal_mask 
-                [/list]
+                [br] 5:0 -- caliptra core non fatal errors
+                [br] {5'b0, cptra_error_non_fatal}
+                [br] 11:6 - mcu non fatal errors
+                [br] {5'b0, mcu_dccm_ecc_single_error}
+                [br] 17:12 -- lcc alerts - masked by default, unmasked in fatal error register
+                [br] {3'b0, fatal_bus_integ_error, fatal_state_error, fatal_prog_error}
+                [br] 23:18 -- otp fc alerts - masked by default, unmasked in fatal error register
+                [br] {1'b0, recov_prim_otp_alert, fatal_prim_otp_alert, fatal_bus_integ_error, fatal_check_error, fatal_macro_error}
+                [br] 29:24 -- I3C
+                [br] {4'b0, i3c_peripheral_reset, i3c_escalated_reset}
+                [br] 31:30 -- spare bits
                 [br]AXI Access:      RW1C
                 [br]TAP Access [with debug intent set]: RO";
         rw_rw_sticky_hw agg_error_non_fatal31 = 1'b0;
@@ -463,24 +477,24 @@ addrmap mci_reg {
                 interrupt.";
         rw_ro_ro_hw mask_agg_error_fatal31 = 1'b0;
         rw_ro_ro_hw mask_agg_error_fatal30 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal29 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal28 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal27 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal26 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal25 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal24 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal23 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal22 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal21 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal20 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal19 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal18 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal17 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal16 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal15 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal14 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal13 = 1'b0;
-        rw_ro_ro_hw mask_agg_error_fatal12 = 1'b0;
+        rw_ro_ro_hw mask_agg_error_fatal29 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal28 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal27 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal26 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal25 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal24 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal23 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal22 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal21 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal20 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal19 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal18 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal17 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal16 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal15 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal14 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal13 = 1'b1;
+        rw_ro_ro_hw mask_agg_error_fatal12 = 1'b1;
         rw_ro_ro_hw mask_agg_error_fatal11 = 1'b0;
         rw_ro_ro_hw mask_agg_error_fatal10 = 1'b0;
         rw_ro_ro_hw mask_agg_error_fatal9  = 1'b0;