[RTL][VAL] MCU TB Trace Testing + MCI interrupt fixes + MCI AXI miss response change

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-057d357cfb7e972bc3d632f418e3161998655e94fafba3d625cccce3ed7e5fbca0f6b326a7f2ee536b07b00446689f72
+c047142f01e0007d1aa78b67fef2147df9dd1c2004ddb954286d4f6adb7bd0e23b8b5b7904594d8cfa332629043b7f3e

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1744958904
+1745004616

docs/CaliptraSSIntegrationSpecification.md

@@ -357,6 +357,7 @@ File at path includes parameters and defines for Caliptra Subystem `src/integrat
 | External | output    | 1     | `ready_for_fuses`                    | Ready for fuses output                   |
 | External | output    | 1     | `ready_for_mb_processing`            | Ready for mailbox processing output      |
 | External | output    | 1     | `mailbox_data_avail`                 | Mailbox data available output            |
+| External | output    | 1     | `cptra_ss_cpu_halt_status_o`                 | MCU Halt status            |
 
 ## Integration Requirements
 
@@ -1072,13 +1073,13 @@ If there is an issue within MCI whether it be the Boot Sequencer or another comp
 
 - Top Level Memory Map
 
-| Internal Block | Address Offset (from base address) | 
-| :---- | :---- | 
-| CSRs | 0x0 |
-| MCU Trace Buffer | 0x10000 |
-| Mailbox 0 | 0x400000|
-| Mailbox 1 | 0x800000|
-| MCU SRAM | 0xC00000 |
+| Internal Block | Address Offset (from base address) | End Address| 
+| :---- | :---- | :---- |
+| CSRs | 0x0 | 0x1FFF | 
+| MCU Trace Buffer | 0x10000 | 0x1001F |
+| Mailbox 0 | 0x400000| 0x7FFFFF |
+| Mailbox 1 | 0x800000| 0xBFFFFF |
+| MCU SRAM | 0xC00000 | MCU SRAM BASE + MCU_SRAM_SIZE |
 
 - MCU SRAM Memory Map
 
@@ -1123,7 +1124,7 @@ The two regions have different access protection. The size of the regions is dyn
 
       To calculate the base address alignment use the following calculation:
 
-        bits = $clog2(MCU_SRAM_OFFSET + ((MCU\_SRAM\_SIZE\_KB * 1024) - 1))
+        bits = $clog2(MCU_SRAM_OFFSET + ((MCU_SRAM_SIZE_KB * 1024) - 1))
 
       MCU\_SRAM\_OFFSET can be found in the MCI’s [Top Level Memory Map](#top-level-memory-map).
 
@@ -1133,7 +1134,7 @@ The two regions have different access protection. The size of the regions is dyn
 
         MCU_SRAM_SIZE_KB = 512 (512KB)
 
-        bits = $clog2(2097152 + ((512 * 1024) - 1)
+        bits = $clog2(12582912 + ((512 * 1024) - 1))
 
         bits = 24
 

src/integration/rtl/caliptra_ss_includes.svh

@@ -31,9 +31,7 @@ parameter CPTRA_SS_ROM_MEM_ADDR_W = $clog2(CPTRA_SS_ROM_DEPTH);
 // Interrupt Assignments
 // NOTE Vector 0 is reserved by VeeR
 `define VEER_INTR_VEC_MCI                 1
-`define VEER_INTR_VEC_CLP_MBOX_DATA_AVAIL 2
-`define VEER_INTR_VEC_I3C                 3
-`define VEER_INTR_VEC_FC                  4
-`define VEER_INTR_EXT_LSB                 5
+`define VEER_INTR_VEC_I3C                 2
+`define VEER_INTR_EXT_LSB                 3
 
 `endif // CPTRA_SS_INCLUDES_SVH

src/integration/rtl/caliptra_ss_top.sv

@@ -159,10 +159,11 @@ module caliptra_ss_top
 `endif
 
 // Caliptra SS MCU 
-    input logic [31:0] cptra_ss_strap_mcu_lsu_axi_user_i,
-    input logic [31:0] cptra_ss_strap_mcu_ifu_axi_user_i,
-    input logic [31:0] cptra_ss_strap_mcu_sram_config_axi_user_i,
-    input logic [31:0] cptra_ss_strap_mci_soc_config_axi_user_i,
+    input  logic [31:0] cptra_ss_strap_mcu_lsu_axi_user_i,
+    input  logic [31:0] cptra_ss_strap_mcu_ifu_axi_user_i,
+    input  logic [31:0] cptra_ss_strap_mcu_sram_config_axi_user_i,
+    input  logic [31:0] cptra_ss_strap_mci_soc_config_axi_user_i,
+    output logic        cptra_ss_cpu_halt_status_o,
 
 // Caliptra SS MCI MCU SRAM Interface (SRAM, MBOX0, MBOX1)
     mci_mcu_sram_if.request cptra_ss_mci_mcu_sram_req_if,
@@ -260,6 +261,7 @@ module caliptra_ss_top
     logic                       mcu_dccm_ecc_single_error;
     logic                       mcu_dccm_ecc_double_error;
 
+    logic                       i3c_irq_o;
     logic                       i3c_peripheral_reset;
     logic                       i3c_escalated_reset;
 
@@ -271,7 +273,6 @@ module caliptra_ss_top
     logic                       jtag_tdo;
     logic                       i_cpu_halt_req;
     logic                       o_cpu_halt_ack;
-    logic                       o_cpu_halt_status;
     logic                       o_cpu_run_ack;
 
     logic        [63:0]         dma_hrdata       ;
@@ -361,7 +362,7 @@ module caliptra_ss_top
     logic [31:0] mci_mcu_nmi_vector;
     logic mci_mcu_timer_int;
 
-    logic [lc_ctrl_reg_pkg::NumAlerts-1:0] lc_alerts_o;  // FIXME: This needs to be an input of MCI
+    logic [lc_ctrl_reg_pkg::NumAlerts-1:0] lc_alerts_o; 
 
     // ----------------- FC to Caliptra-Core ports -----------------------
     otp_ctrl_part_pkg::otp_broadcast_t from_otp_to_clpt_core_broadcast;  // This is a struct data type
@@ -559,23 +560,21 @@ module caliptra_ss_top
 
     //Interrupt connections
     assign ext_int[`VEER_INTR_VEC_MCI]                  = mci_intr;
-    assign ext_int[`VEER_INTR_VEC_CLP_MBOX_DATA_AVAIL]  = mailbox_data_avail;
-    assign ext_int[`VEER_INTR_VEC_I3C]                  = 0;
-    assign ext_int[`VEER_INTR_VEC_FC]                   = intr_otp_operation_done;
+    assign ext_int[`VEER_INTR_VEC_I3C]                  = i3c_irq_o;
     assign ext_int[pt.PIC_TOTAL_INT:`VEER_INTR_EXT_LSB] = cptra_ss_mcu_ext_int;
 
     //Aggregate error connections
     assign agg_error_fatal[5:0]   = {5'b0, cptra_error_fatal}; //CPTRA
     assign agg_error_fatal[11:6]  = {5'b0, mcu_dccm_ecc_double_error}; //MCU
     assign agg_error_fatal[17:12] = {{6-lc_ctrl_reg_pkg::NumAlerts{1'b0}}, lc_alerts_o}; //LCC
-    assign agg_error_fatal[23:18] = {{6-otp_ctrl_reg_pkg::NumAlerts{1'b0}}, fc_alerts}; //FC
+    assign agg_error_fatal[23:18] = {fc_intr_otp_error, fc_alerts}; //FC
     assign agg_error_fatal[29:24] = {4'b0, i3c_peripheral_reset, i3c_escalated_reset}; //I3C
     assign agg_error_fatal[31:30] = '0; //spare
 
     assign agg_error_non_fatal[5:0]   = {5'b0, cptra_error_non_fatal}; //CPTRA
     assign agg_error_non_fatal[11:6]  = {5'b0, mcu_dccm_ecc_single_error}; //MCU
     assign agg_error_non_fatal[17:12] = {{6-lc_ctrl_reg_pkg::NumAlerts{1'b0}}, lc_alerts_o}; //LCC
-    assign agg_error_non_fatal[23:18] = {{6-otp_ctrl_reg_pkg::NumAlerts{1'b0}}, fc_alerts}; //FC
+    assign agg_error_non_fatal[23:18] = {fc_intr_otp_error, fc_alerts}; //FC
     assign agg_error_non_fatal[29:24] = {4'b0, i3c_peripheral_reset, i3c_escalated_reset}; //I3C
     assign agg_error_non_fatal[31:30] = '0; //spare
 
@@ -803,7 +802,7 @@ module caliptra_ss_top
 
         .i_cpu_halt_req         ( i_cpu_halt_req ),    // Async halt req to CPU
         .o_cpu_halt_ack         ( o_cpu_halt_ack ),    // core response to halt
-        .o_cpu_halt_status      ( o_cpu_halt_status ), // 1'b1 indicates core is halted
+        .o_cpu_halt_status      ( cptra_ss_cpu_halt_status_o ), // 1'b1 indicates core is halted
         .i_cpu_run_req          ( 1'b0  ),     // Async restart req to CPU
         .o_cpu_run_ack          ( o_cpu_run_ack ),     // Core response to run req
 
@@ -933,9 +932,8 @@ module caliptra_ss_top
         .peripheral_reset_o(i3c_peripheral_reset),
         .peripheral_reset_done_i(1'b1),
         .escalated_reset_o(i3c_escalated_reset),
-        .irq_o()
+        .irq_o(i3c_irq_o)
 
-    // TODO: Add interrupts
     );
 
     //=========================================================================
@@ -1020,10 +1018,14 @@ module caliptra_ss_top
         .strap_mcu_reset_vector(cptra_ss_strap_mcu_reset_vector_i),
 
         .mcu_reset_vector(reset_vector),
+
+        // OTP
+        .intr_otp_operation_done,
+
         // MCU Halt Signals
         .mcu_cpu_halt_req_o   (i_cpu_halt_req   ),
         .mcu_cpu_halt_ack_i   (o_cpu_halt_ack   ),
-        .mcu_cpu_halt_status_i(o_cpu_halt_status),
+        .mcu_cpu_halt_status_i(cptra_ss_cpu_halt_status_o),
 
         .mcu_no_rom_config(cptra_ss_mcu_no_rom_config_i),
 
@@ -1208,7 +1210,7 @@ module caliptra_ss_top
         .prim_generic_otp_inputs_o  (cptra_ss_fuse_macro_inputs_o),
 
         .intr_otp_operation_done_o  (intr_otp_operation_done),
-        .intr_otp_error_o           (fc_intr_otp_error), //TODO: This signal should be connected to MCI
+        .intr_otp_error_o           (fc_intr_otp_error), 
         // .alert_rx_i                 (),
         // .alert_tx_o                 (),
         .alerts(fc_alerts),

src/integration/rtl/soc_address_map.h

@@ -7784,6 +7784,8 @@
 #define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX0_SOC_REQ_LOCK_EN_MASK                     (0x1000)
 #define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX1_SOC_REQ_LOCK_EN_LOW                      (13)
 #define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX1_SOC_REQ_LOCK_EN_MASK                     (0x2000)
+#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_OTP_OPERATION_DONE_EN_LOW                      (14)
+#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_OTP_OPERATION_DONE_EN_MASK                     (0x4000)
 #endif
 #define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_EN_R                                          (0x21001010)
 #ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_EN_R
@@ -7984,6 +7986,8 @@
 #define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX0_SOC_REQ_LOCK_STS_MASK              (0x1000)
 #define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX1_SOC_REQ_LOCK_STS_LOW               (13)
 #define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX1_SOC_REQ_LOCK_STS_MASK              (0x2000)
+#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_OTP_OPERATION_DONE_STS_LOW               (14)
+#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_OTP_OPERATION_DONE_STS_MASK              (0x4000)
 #endif
 #define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF1_INTERNAL_INTR_R                                    (0x21001028)
 #ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTERNAL_INTR_R
@@ -8168,6 +8172,8 @@
 #define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX0_SOC_REQ_LOCK_TRIG_MASK                 (0x1000)
 #define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX1_SOC_REQ_LOCK_TRIG_LOW                  (13)
 #define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX1_SOC_REQ_LOCK_TRIG_MASK                 (0x2000)
+#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_OTP_OPERATION_DONE_TRIG_LOW                  (14)
+#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_OTP_OPERATION_DONE_TRIG_MASK                 (0x4000)
 #endif
 #define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_TRIG_R                                        (0x21001038)
 #ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_TRIG_R
@@ -8573,6 +8579,10 @@
 #ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_R
 #define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_R                                 (0x12b4)
 #endif
+#define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R                     (0x210012b8)
+#ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R
+#define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R                                 (0x12b8)
+#endif
 #define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R                          (0x21001300)
 #ifndef MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R
 #define MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R                                      (0x1300)
@@ -9077,6 +9087,12 @@
 #define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_LOW                  (0)
 #define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK                 (0x1)
 #endif
+#define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R                (0x21001450)
+#ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R
+#define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R                            (0x1450)
+#define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R_PULSE_LOW                  (0)
+#define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R_PULSE_MASK                 (0x1)
+#endif
 #define SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_BASE_ADDR                                                  (0x21010000)
 #define SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_STATUS                                                     (0x21010000)
 #ifndef MCU_TRACE_BUFFER_CSR_STATUS

src/integration/rtl/soc_address_map_defines.svh

@@ -701,6 +701,7 @@
 `define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R                              (32'h210012ac)
 `define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX0_SOC_REQ_LOCK_INTR_COUNT_R                     (32'h210012b0)
 `define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_R                     (32'h210012b4)
+`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R                     (32'h210012b8)
 `define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R                          (32'h21001300)
 `define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR_MBOX0_ECC_UNC_INTR_COUNT_INCR_R                     (32'h21001304)
 `define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR_MBOX1_ECC_UNC_INTR_COUNT_INCR_R                     (32'h21001308)
@@ -785,6 +786,7 @@
 `define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R                         (32'h21001444)
 `define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX0_SOC_REQ_LOCK_INTR_COUNT_INCR_R                (32'h21001448)
 `define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_INCR_R                (32'h2100144c)
+`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R                (32'h21001450)
 `define SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_BASE_ADDR                                                  (32'h21010000)
 `define SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_STATUS                                                     (32'h21010000)
 `define SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_CONFIG                                                     (32'h21010004)

src/integration/rtl/soc_address_map_field_defines.svh

@@ -7194,6 +7194,8 @@
 `define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX0_SOC_REQ_LOCK_EN_MASK                     (32'h1000)
 `define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX1_SOC_REQ_LOCK_EN_LOW                      (13)
 `define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX1_SOC_REQ_LOCK_EN_MASK                     (32'h2000)
+`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_OTP_OPERATION_DONE_EN_LOW                      (14)
+`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_OTP_OPERATION_DONE_EN_MASK                     (32'h4000)
 `endif
 `ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_EN_R
 `define MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_EN_R                                                      (32'h1010)
@@ -7388,6 +7390,8 @@
 `define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX0_SOC_REQ_LOCK_STS_MASK              (32'h1000)
 `define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX1_SOC_REQ_LOCK_STS_LOW               (13)
 `define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX1_SOC_REQ_LOCK_STS_MASK              (32'h2000)
+`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_OTP_OPERATION_DONE_STS_LOW               (14)
+`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_OTP_OPERATION_DONE_STS_MASK              (32'h4000)
 `endif
 `ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTERNAL_INTR_R
 `define MCI_REG_INTR_BLOCK_RF_NOTIF1_INTERNAL_INTR_R                                                (32'h1028)
@@ -7568,6 +7572,8 @@
 `define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX0_SOC_REQ_LOCK_TRIG_MASK                 (32'h1000)
 `define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX1_SOC_REQ_LOCK_TRIG_LOW                  (13)
 `define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX1_SOC_REQ_LOCK_TRIG_MASK                 (32'h2000)
+`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_OTP_OPERATION_DONE_TRIG_LOW                  (14)
+`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_OTP_OPERATION_DONE_TRIG_MASK                 (32'h4000)
 `endif
 `ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_TRIG_R
 `define MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_TRIG_R                                                    (32'h1038)
@@ -7888,6 +7894,9 @@
 `ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_R
 `define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_R                                 (32'h12b4)
 `endif
+`ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R
+`define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R                                 (32'h12b8)
+`endif
 `ifndef MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R
 `define MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R                                      (32'h1300)
 `define MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW                            (0)
@@ -8308,6 +8317,11 @@
 `define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_LOW                  (0)
 `define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK                 (32'h1)
 `endif
+`ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R
+`define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R                            (32'h1450)
+`define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R_PULSE_LOW                  (0)
+`define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R_PULSE_MASK                 (32'h1)
+`endif
 `ifndef MCU_TRACE_BUFFER_CSR_STATUS
 `define MCU_TRACE_BUFFER_CSR_STATUS                                                                 (32'h0)
 `define MCU_TRACE_BUFFER_CSR_STATUS_WRAPPED_LOW                                                     (0)

src/integration/stimulus/L0_Promote_caliptra_ss_top_tb_regression.yml

@@ -26,6 +26,12 @@ contents:
         - ../test_suites/smoke_test_mcu_sram_protected_region/smoke_test_mcu_sram_protected_region.yml
         - ../test_suites/smoke_test_mcu_sram_execution_region/smoke_test_mcu_sram_execution_region.yml
         - ../test_suites/smoke_test_mcu_sram_execution_region/smoke_test_mcu_sram_execution_region_max_size.yml
+        - ../test_suites/smoke_test_mcu_trace_buffer/smoke_test_mcu_trace_buffer.yml
+        - ../test_suites/smoke_test_mcu_trace_buffer/smoke_test_mcu_trace_buffer_single.yml
+        - ../test_suites/smoke_test_mcu_trace_buffer/smoke_test_mcu_trace_buffer_random.yml
+        - ../test_suites/smoke_test_mcu_trace_buffer/smoke_test_mcu_trace_buffer_64.yml
+        - ../test_suites/smoke_test_mcu_trace_buffer/smoke_test_mcu_trace_buffer_63.yml
+        - ../test_suites/smoke_test_mcu_trace_buffer_no_debug/smoke_test_mcu_trace_buffer_no_debug.yml
         - ../test_suites/smoke_test_mcu_mbox_valid_user/smoke_test_mcu_mbox0_valid_user.yml
         - ../test_suites/smoke_test_mcu_mbox_write_user_lock/smoke_test_mcu_mbox0_write_user_lock.yml
         - ../test_suites/smoke_test_mcu_mbox_usr_lock_out_zero/smoke_test_mcu_mbox0_usr_lock_out_zero.yml

src/integration/stimulus/L1_Nightly_Directed_caliptra_ss_top_tb_regression.yml

@@ -6,7 +6,7 @@ contents:
       tags: ["L1", "caliptra_ss_top_tb", "Directed", "Nightly"]
       path: ""
       weight: 100
-      generations: 430
+      generations: 440
       formats:
         generate: "reseed {template}.yml -seed {seed}"
         path: "{template_basename}__{seed}.yml"
@@ -48,6 +48,7 @@ contents:
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_strb_wr_csr/smoke_test_mcu_mbox1_strb_wr_csr: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_kmac_kat/smoke_test_lcc_kmac_kat: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_lcc_st_trans/caliptra_ss_lcc_st_trans: { weight: 100 }
+        $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_lcc_escalation/caliptra_ss_lcc_escalation: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_integrity_check/caliptra_ss_fuse_ctrl_integrity_check: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_registers/smoke_test_lcc_registers: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_bus_ecc_error/caliptra_ss_fuse_ctrl_bus_ecc_error: { weight: 100 }