User/ekarabulut/otp optional items by ekarabu · Pull Request #483 · chipsalliance/caliptra-ss

ekarabu · 2025-05-23T16:15:49Z

Updated FUSE macro map, updated size of FUSE items (IDevID Cert vs Attribute).
Updated documentation and explained optional FUSE partitions/items.
Cleaned up the code space (removing redundant semicolons).
Extended MCI state translation capacity and covered Volatile RAW Unlock state.

This extends the functionality of the `gen_fuse_ctrl_partitions.py` script to also generate Markdown documentation of the register file. In the process, we fix some dead links in the integration specification documentation. Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org>

…updated timestamp and hash after successful run

Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org>

andrea-caforio

Thank you @ekarabu. I removed the hardcoded values from the TB services and fixed the failing tests. The remaining things look good to me.

taku202107 · 2025-05-26T23:43:45Z

Thank you for fixing the size of CPTRA_CORE_IDEVID_CERT_IDEVID_ATTR, but the size in "opt_ctrl_mmap.md" is still 7952B.
Please check it.

Alexandiz · 2025-05-27T06:08:58Z

Hi,
Thank you for fix! I reviewed the changes in updated document [caliptra-ss/src/fuse_ctrl/doc/otp_ctrl_field_descriptions.md at 98ebd3811883d1e6f57c7467b96dfe6918ced2b8 · chipsalliance/caliptra-ss](https://github.com/chipsalliance/caliptra-ss/blob/98ebd3811883d1e6f57c7467b96dfe6918ced2b8/src/fuse_ctrl/doc/otp_ctrl_field_descriptions.md) . These are new opens:

CPTRA_SS_OWNER_PQC_KEY_TYPE1..15 – missing in the list. Exist only index ‘0’
CPTRA_SS_OWNER_PK_HASH1..15 – missing in the list. Exist only index ‘0’
CPTRA_SS_OWNER_MLDSA_REVOCATION_1..15 - missing in the list. Exist only index ‘0’
CPTRA_SS_OWNER_ECC_REVOCATION_1..15 - missing in the list. Exist only index ‘0’
CPTRA_SS_OWNER_PK_HASH_VALID - shall cover 16 keys, not 1 (shall be 2 bytes)
CPTRA_SS_OWNER_LMS_REVOCATION_0..15 – why it is not 1 bit per key x 16 keys? (2 bytes total)
CPTRA_CORE_ECC_REVOCATION_0..15 - why it is not 1 bit per key x 16 keys? (2 bytes total)
CPTRA_CORE_LMS_REVOCATION_0..15 - why it is not 1 bit per key x 16 keys? (2 bytes total)
CPTRA_CORE_MLDSA_REVOCATION_0..15 - why it is not 1 bit per key x 16 keys? (2 bytes total)
missing:

CPTRA_CORE_UDS_SEED
CPTRA_CORE_FIELD_ENTROPY_0 .. 3
LC_TRANSITION_CNT
csr_mode

andrea-caforio · 2025-05-27T07:08:18Z

Thank you for fixing the size of CPTRA_CORE_IDEVID_CERT_IDEVID_ATTR, but the size in "opt_ctrl_mmap.md" is still 7952B. Please check it.

Where do you see that? It's 96 bytes here:

caliptra-ss/src/fuse_ctrl/doc/otp_ctrl_mmap.md

Line 20 in b0548ff

    
           |         |                                   |            |      32bit       |                             CPTRA_CORE_IDEVID_CERT_IDEVID_ATTR                              |     0x0D1      |     96     |

taku202107 · 2025-05-27T07:21:42Z

Thank you for fixing the size of CPTRA_CORE_IDEVID_CERT_IDEVID_ATTR, but the size in "opt_ctrl_mmap.md" is still 7952B. Please check it.

Where do you see that? It's 96 bytes here:

caliptra-ss/src/fuse_ctrl/doc/otp_ctrl_mmap.md

Line 20 in b0548ff

| | | | 32bit | CPTRA_CORE_IDEVID_CERT_IDEVID_ATTR | 0x0D1 | 96 |

Sorry for my ambiguous comment. Please check "Preview" page of opt_ctrl_mmap.md.

andrea-caforio · 2025-05-27T07:35:49Z

Thank you for fixing the size of CPTRA_CORE_IDEVID_CERT_IDEVID_ATTR, but the size in "opt_ctrl_mmap.md" is still 7952B. Please check it.

Where do you see that? It's 96 bytes here:

caliptra-ss/src/fuse_ctrl/doc/otp_ctrl_mmap.md

Line 20 in b0548ff

| | | | 32bit | CPTRA_CORE_IDEVID_CERT_IDEVID_ATTR | 0x0D1 | 96 |

Sorry for my ambiguous comment. Please check "Preview" page of opt_ctrl_mmap.md.

Can you give a me link to where it is 7952? :-) In this PR it's 96.

taku202107 · 2025-05-27T07:50:18Z

Thank you for fixing the size of CPTRA_CORE_IDEVID_CERT_IDEVID_ATTR, but the size in "opt_ctrl_mmap.md" is still 7952B. Please check it.

Where do you see that? It's 96 bytes here:

caliptra-ss/src/fuse_ctrl/doc/otp_ctrl_mmap.md

Line 20 in b0548ff

| | | | 32bit | CPTRA_CORE_IDEVID_CERT_IDEVID_ATTR | 0x0D1 | 96 |

Sorry for my ambiguous comment. Please check "Preview" page of opt_ctrl_mmap.md.

Can you give a me link to where it is 7952? :-) In this PR it's 96.

Please check the index 6 of the following link:
https://github.com/chipsalliance/caliptra-ss/blob/main/src/fuse_ctrl/doc/otp_ctrl_mmap.md

You are referring to the main branch where it is still 7982. This PR has not been merged yet. Once it is it will also be correct on the main branch.

Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org>

Alexandiz · 2025-05-28T15:57:14Z

CPTRA_CORE_UDS_SEED

CPTRA_CORE_FIELD_ENTROPY_0 .. 3

LC_TRANSITION_CNT

csr_mode

Please review https://github.com/chipsalliance/caliptra-ss/blob/main/src/fuse_ctrl/doc/otp_ctrl_mmap.md

CPTRA_CORE_UDS_SEED, CPTRA_CORE_FIELD_ENTROPY_0 .. 3, LC_TRANSITION_CNT present in otp_ctrl_mmap.md, but missing in otp_ctrl_field_descriptions.md
csr_mode is missing in both otp_ctrl_mmap.md and otp_ctrl_field_descriptions.md

bharatpillilli · 2025-05-28T16:05:46Z

"csr_mode is missing in both otp_ctrl_mmap.md and otp_ctrl_field_descriptions.md" -> Can you please explain?

Alexandiz · 2025-05-28T16:37:28Z

"csr_mode is missing in both otp_ctrl_mmap.md and otp_ctrl_field_descriptions.md" -> Can you please explain?
I read again the specifications and looks like CSR_MODE is not an OTP setting, but a software-writeable bit in the HMAC control register.
I assume it is SOC decision if CSR Mode is enabled or not. I think it would be more convenience to handle it as OTP setting.
what do you think?

bharatpillilli · 2025-05-28T16:48:46Z

"csr_mode is missing in both otp_ctrl_mmap.md and otp_ctrl_field_descriptions.md" -> Can you please explain?
I read again the specifications and looks like CSR_MODE is not an OTP setting, but a software-writeable bit in the HMAC control register.
I assume it is SOC decision if CSR Mode is enabled or not. I think it would be more convenience to handle it as OTP setting.
what do you think?

Are you talking about HMAC operations within Caliptra core? If so, please check Caliptra RT FW on the APIs and modes it has in terms of the current usage. from HW point of view, its a write-only register and Caliptra RT FW controls it and it controls the externally available APIs -> https://chipsalliance.github.io/caliptra-rtl/main/internal-regs/?p=clp.hmac_reg.HMAC512_CTRL

bharatpillilli · 2025-05-28T16:49:51Z

@Alexandiz - can you please state your affiliation/company since its not obvious from your githubID?

…/chipsalliance/caliptra-ss into user/ekarabulut/otp_optional_items

…ms' with updated timestamp and hash after successful run

Alexandiz · 2025-05-29T06:20:41Z

@Alexandiz - can you please state your affiliation/company since its not obvious from your githubID?

Sure. I updated profile and contacted you over slack

Alexandiz · 2025-05-29T06:21:52Z

"csr_mode is missing in both otp_ctrl_mmap.md and otp_ctrl_field_descriptions.md" -> Can you please explain?
I read again the specifications and looks like CSR_MODE is not an OTP setting, but a software-writeable bit in the HMAC control register.
I assume it is SOC decision if CSR Mode is enabled or not. I think it would be more convenience to handle it as OTP setting.
what do you think?

Are you talking about HMAC operations within Caliptra core? If so, please check Caliptra RT FW on the APIs and modes it has in terms of the current usage. from HW point of view, its a write-only register and Caliptra RT FW controls it and it controls the externally available APIs -> https://chipsalliance.github.io/caliptra-rtl/main/internal-regs/?p=clp.hmac_reg.HMAC512_CTRL

@bharatpillilli ,
How you suggest to discuss this flow E2E? over slack? in this thread? in weekly meeting?
Thank you

bharatpillilli · 2025-05-29T07:19:20Z

"csr_mode is missing in both otp_ctrl_mmap.md and otp_ctrl_field_descriptions.md" -> Can you please explain?
I read again the specifications and looks like CSR_MODE is not an OTP setting, but a software-writeable bit in the HMAC control register.
I assume it is SOC decision if CSR Mode is enabled or not. I think it would be more convenience to handle it as OTP setting.
what do you think?

Are you talking about HMAC operations within Caliptra core? If so, please check Caliptra RT FW on the APIs and modes it has in terms of the current usage. from HW point of view, its a write-only register and Caliptra RT FW controls it and it controls the externally available APIs -> https://chipsalliance.github.io/caliptra-rtl/main/internal-regs/?p=clp.hmac_reg.HMAC512_CTRL

@bharatpillilli , How you suggest to discuss this flow E2E? over slack? in this thread? in weekly meeting? Thank you

Plz open a GitHub issue. Further hmac is not exposed to SoC for random injections. It would be best to look through the spec one more time before filing the issue itself.

docs/CaliptraSSHardwareSpecification.md

Alexandiz · 2025-05-29T19:42:45Z

@bharatpillilli ,
@bharatpillilli
I opened this issue: chipsalliance/Caliptra#374
Thank you

…ms' with updated timestamp and hash after successful run

andrea-caforio and others added 6 commits May 21, 2025 05:58

MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_fix_fuse_ctrl_doc' with …

b5b3444

…updated timestamp and hash after successful run

merged with main

33b7f75

merged with main

126bc8b

updated fuse map

d9a7fe4

removed an unused assertion

3b15112

ekarabu mentioned this pull request May 23, 2025

Remove assetoff for LCC translator #410

Closed

Resolved Issue #439

1251491

ekarabu mentioned this pull request May 23, 2025

CALIPTRA_ASSERTs should not end with a semicolon #439

Closed

ekarabu added 5 commits May 23, 2025 11:05

clarified FIPS zeroization flow

e9c5642

added details on optional fuses

7b9fce7

Resolved Issue #441

9a770e1

Resolved issue #441 2

fda7eff

fixed naming

3ec2497

This was referenced May 23, 2025

Size of CPTR_CORE_IDEVID_CERT_IDEVID_ATTR #432

Closed

Total size of OTP bits requirements #420

Closed

ekarabu added 3 commits May 23, 2025 14:25

updated partition number in the doc

bc96efd

Merge branch 'main' into user/ekarabulut/otp_optional_items

29437f2

added owner PK hash

98ebd38

ekarabu mentioned this pull request May 23, 2025

mismatch on Fuse map definition #438

Closed

[fuse_ctrl, test] Remove hardcoded addresses from tb services

d4e2131

Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org>

andrea-caforio previously approved these changes May 25, 2025

View reviewed changes

[fuse_ctrl, rtl] Make pk hash vendor lock more generic

38f6bdc

Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org>

andrea-caforio dismissed their stale review via 38f6bdc May 27, 2025 09:08

andrea-caforio previously approved these changes May 28, 2025

View reviewed changes

bharatpillilli previously approved these changes May 28, 2025

View reviewed changes

ekarabu added 2 commits May 28, 2025 12:03

Resolved #463

f2cfeb4

Merge branch 'user/ekarabulut/otp_optional_items' of ssh://github.com…

9b72d28

…/chipsalliance/caliptra-ss into user/ekarabulut/otp_optional_items

ekarabu dismissed stale reviews from bharatpillilli and andrea-caforio via 9b72d28 May 28, 2025 19:03

nileshbpat previously approved these changes May 28, 2025

View reviewed changes

MICROSOFT AUTOMATED PIPELINE: Stamp 'user/ekarabulut/otp_optional_ite…

cce9b92

…ms' with updated timestamp and hash after successful run

nileshbpat dismissed their stale review via cce9b92 May 29, 2025 02:03

ekarabu commented May 29, 2025

View reviewed changes

docs/CaliptraSSHardwareSpecification.md Outdated Show resolved Hide resolved

bharatpillilli previously approved these changes May 29, 2025

View reviewed changes

merged main

a46ebbd

ekarabu dismissed bharatpillilli’s stale review via a46ebbd May 30, 2025 19:53

ekarabu and others added 2 commits May 30, 2025 12:59

extended scan path excl list

c3ce1c0

MICROSOFT AUTOMATED PIPELINE: Stamp 'user/ekarabulut/otp_optional_ite…

a99d1c6

…ms' with updated timestamp and hash after successful run

bharatpillilli approved these changes May 30, 2025

View reviewed changes

ekarabu merged commit cfc6547 into main May 30, 2025
8 checks passed

ekarabu deleted the user/ekarabulut/otp_optional_items branch May 30, 2025 21:12

This was referenced Jun 4, 2025

[fuse_ctrl, doc] Add register doc generation to partition script #472

Closed

[mci, rtl] Remove leftover assertoff #475

Closed

RaunakGu mentioned this pull request Jun 12, 2025

Where and How owner PK Hash being defined chipsalliance/caliptra-sw#2183

Open

Conversation

ekarabu commented May 23, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

andrea-caforio left a comment

Choose a reason for hiding this comment

Uh oh!

taku202107 commented May 26, 2025

Uh oh!

Alexandiz commented May 27, 2025

Uh oh!

andrea-caforio commented May 27, 2025

Uh oh!

taku202107 commented May 27, 2025

Uh oh!

andrea-caforio commented May 27, 2025

Uh oh!

taku202107 commented May 27, 2025 • edited by andrea-caforio Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

Alexandiz commented May 28, 2025

Uh oh!

bharatpillilli commented May 28, 2025

Uh oh!

Alexandiz commented May 28, 2025

Uh oh!

bharatpillilli commented May 28, 2025

Uh oh!

bharatpillilli commented May 28, 2025

Uh oh!

Alexandiz commented May 29, 2025

Uh oh!

Alexandiz commented May 29, 2025

Uh oh!

bharatpillilli commented May 29, 2025

Uh oh!

Uh oh!

Alexandiz commented May 29, 2025

Uh oh!

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

6 participants

ekarabu commented May 23, 2025 •

edited

Loading

taku202107 commented May 27, 2025 •

edited by andrea-caforio

Loading