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Update integration and HW spec#734

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clayton8 merged 8 commits intomainfrom
ckuchta-update-doc
Sep 17, 2025
Merged

Update integration and HW spec#734
clayton8 merged 8 commits intomainfrom
ckuchta-update-doc

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@clayton8 clayton8 commented Sep 17, 2025

  • Add note about MCU MBOX DLEN 0 SRAM clearing behavior
  • Add external staging area strap
  • Update SOC usage of generic input/output wires
  • Remove FIPS_ZEROIZATION_PPD_i generic input wire usage since port exist on CSS
  • Add generic output wire usage table

@clayton8 clayton8 requested a review from Copilot September 17, 2025 15:13
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Pull Request Overview

This PR updates integration and hardware specification documentation to clarify mailbox behavior and add external staging area configuration. The changes focus on improving clarity around MBOX SRAM clearing behavior when DLEN=0 and documenting the external staging area strap configuration.

  • Add clarification about MCU MBOX DLEN 0 SRAM clearing behavior and workaround
  • Add external staging area strap configuration parameter
  • Update MCI generic input wire allocation guidance

Reviewed Changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 2 comments.

File Description
docs/CaliptraSSIntegrationSpecification.md Adds external staging area strap parameter, new MCU mailbox DLEN section, and updates generic wire allocation guidance
docs/CaliptraSSHardwareSpecification.md Adds note about DLEN=0 causing entire MBOX SRAM clearing

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calebofearth
calebofearth previously approved these changes Sep 17, 2025
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Pull Request Overview

Copilot reviewed 2 out of 2 changed files in this pull request and generated 1 comment.


Tip: Customize your code reviews with copilot-instructions.md. Create the file or learn how to get started.

@clayton8 clayton8 merged commit 3952ef9 into main Sep 17, 2025
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clayton8 added a commit that referenced this pull request Oct 3, 2025
* Update late binding interface signals section

MCI generic input wires are allowed to be used by the SOC.

* Add MCU Mailbox Doorbell Command DLEN section

* Add MCU MBOX DLEN 0 clears entire MBOX SRAM

* Add external staging area base address input

* Fix typo in note about MBOX SRAM clearing

* Revise mci_generic_input/output wires allocation details

* Update docs/CaliptraSSIntegrationSpecification.md

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* Correct capitalization of 'Chips Alliance' to 'CHIPS Alliance'

---------

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
clayton8 added a commit that referenced this pull request Oct 10, 2025
* Update late binding interface signals section

MCI generic input wires are allowed to be used by the SOC.

* Add MCU Mailbox Doorbell Command DLEN section

* Add MCU MBOX DLEN 0 clears entire MBOX SRAM

* Add external staging area base address input

* Fix typo in note about MBOX SRAM clearing

* Revise mci_generic_input/output wires allocation details

* Update docs/CaliptraSSIntegrationSpecification.md

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* Correct capitalization of 'Chips Alliance' to 'CHIPS Alliance'

---------

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
calebofearth added a commit that referenced this pull request Oct 10, 2025
* Update integration and HW spec (#734)

* Update late binding interface signals section

MCI generic input wires are allowed to be used by the SOC.

* Add MCU Mailbox Doorbell Command DLEN section

* Add MCU MBOX DLEN 0 clears entire MBOX SRAM

* Add external staging area base address input

* Fix typo in note about MBOX SRAM clearing

* Revise mci_generic_input/output wires allocation details

* Update docs/CaliptraSSIntegrationSpecification.md

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* Correct capitalization of 'Chips Alliance' to 'CHIPS Alliance'

---------

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* [DOC] Add MCU Customization (#748)

* [DOC] Add MCU customization

* Clean up README by removing configuration examples

Removed common configuration examples and troubleshooting tips from README.

* [DOC] Add additional lint exceptions (#765)

* [DOC] Add MCU icache and DCCM sizing requirements (#771)

* [DOC] Add MCU iCache requirements

* Fix spelling and clarify MCU iCache requirements

Corrected spelling errors and clarified MCU iCache integration requirements.

* Update docs/CaliptraSSIntegrationSpecification.md

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

* [Doc] Add DCCM sizing note

* Update docs/CaliptraSSIntegrationSpecification.md

Co-authored-by: Christopher Swenson <swenson@swenson.io>

* Modify MCI Register Space mapping requirements

Updated MCI Register Space mapping to enable side effects.

* Add side effect info for SRAMs used by MCU

* Update DWORD access requirements in specification

Clarified DWORD access requirements and split memory mapping options.

---------

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Christopher Swenson <swenson@swenson.io>

* Clarify AXI interface usage in Caliptra Core

* Update docs/CaliptraSSIntegrationSpecification.md

Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com>

* Update docs/CaliptraSSIntegrationSpecification.md

Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com>

* Update docs/CaliptraSSIntegrationSpecification.md

Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com>

---------

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Christopher Swenson <swenson@swenson.io>
Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com>
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3 participants