[DOC] Add MCU icache and DCCM sizing requirements#771
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Pull Request Overview
This pull request adds documentation for MCU iCache integration requirements to the Caliptra SS Integration Specification. The documentation explains the memory mapping constraints needed when implementing MCU instruction cache functionality.
- Added a new section detailing MCU iCache integration requirements
- Updated table of contents to include the new section
- Documented memory mapping requirements for cache-enabled implementations
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swenson
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Sep 29, 2025
clayton8
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swenson
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Sep 29, 2025
Corrected spelling errors and clarified MCU iCache integration requirements.
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Christopher Swenson <swenson@swenson.io>
Updated MCI Register Space mapping to enable side effects.
Clarified DWORD access requirements and split memory mapping options.
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* [DOC] Add MCU iCache requirements * Fix spelling and clarify MCU iCache requirements Corrected spelling errors and clarified MCU iCache integration requirements. * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * [Doc] Add DCCM sizing note * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Christopher Swenson <swenson@swenson.io> * Modify MCI Register Space mapping requirements Updated MCI Register Space mapping to enable side effects. * Add side effect info for SRAMs used by MCU * Update DWORD access requirements in specification Clarified DWORD access requirements and split memory mapping options. --------- Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> Co-authored-by: Christopher Swenson <swenson@swenson.io>
clayton8
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Oct 10, 2025
* [DOC] Add MCU iCache requirements * Fix spelling and clarify MCU iCache requirements Corrected spelling errors and clarified MCU iCache integration requirements. * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * [Doc] Add DCCM sizing note * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Christopher Swenson <swenson@swenson.io> * Modify MCI Register Space mapping requirements Updated MCI Register Space mapping to enable side effects. * Add side effect info for SRAMs used by MCU * Update DWORD access requirements in specification Clarified DWORD access requirements and split memory mapping options. --------- Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> Co-authored-by: Christopher Swenson <swenson@swenson.io>
calebofearth
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Oct 10, 2025
* Update integration and HW spec (#734) * Update late binding interface signals section MCI generic input wires are allowed to be used by the SOC. * Add MCU Mailbox Doorbell Command DLEN section * Add MCU MBOX DLEN 0 clears entire MBOX SRAM * Add external staging area base address input * Fix typo in note about MBOX SRAM clearing * Revise mci_generic_input/output wires allocation details * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Correct capitalization of 'Chips Alliance' to 'CHIPS Alliance' --------- Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * [DOC] Add MCU Customization (#748) * [DOC] Add MCU customization * Clean up README by removing configuration examples Removed common configuration examples and troubleshooting tips from README. * [DOC] Add additional lint exceptions (#765) * [DOC] Add MCU icache and DCCM sizing requirements (#771) * [DOC] Add MCU iCache requirements * Fix spelling and clarify MCU iCache requirements Corrected spelling errors and clarified MCU iCache integration requirements. * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * [Doc] Add DCCM sizing note * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Christopher Swenson <swenson@swenson.io> * Modify MCI Register Space mapping requirements Updated MCI Register Space mapping to enable side effects. * Add side effect info for SRAMs used by MCU * Update DWORD access requirements in specification Clarified DWORD access requirements and split memory mapping options. --------- Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> Co-authored-by: Christopher Swenson <swenson@swenson.io> * Clarify AXI interface usage in Caliptra Core * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> --------- Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> Co-authored-by: Christopher Swenson <swenson@swenson.io> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com>
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